Timing based camouflage circuit

Patent metadata

Field	Value
Publication number	US-2018247902-A1
Application number	US-201715640615-A
Country	US
Kind code	A1
Filing date	Jul 3, 2017
Priority date	Feb 27, 2017
Publication date	Aug 30, 2018
Grant date	—

Abstract

In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.

First claim

What is claimed is:

1 . A chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.

2 . The chip of claim 1 , wherein the plurality of components includes one or more components that are substantially the same as at least one component that would be in at least one corresponding position in the other circuit.

3 . The chip of claim 1 , wherein the plurality of components includes at least one component that has a geometry that is substantially the same but has a different timing behavior than one or more components that would be in one or more corresponding positions in the other circuit.

4 . The chip of claim 1 , wherein the plurality of components includes at least one component selected from a pool of components characterized by substantially the same geometries but varied timing behaviors, the at least one component characterized by timing behavior suitable for implementing the timing behavior of the circuit.

5 . The chip of claim 4 , wherein the plurality of components includes at least one other component selected from the pool, the at least one other component characterized by other timing behavior suitable for implementing the timing behavior of the circuit.

6 . The chip of claim 5 , wherein a quantity and a positioning of said at least one component and said at least one other component are suitable for implementing the timing behavior of the circuit.

7 . The chip of claim 4 , wherein said pool of components includes buffer cells.

8 . The chip of claim 1 , wherein the circuit is asynchronous.

9 . The chip of claim 1 , including a plurality of the circuit.

10 . A chip comprising:
a first circuit including a first plurality of components, the first circuit adapted to perform a function that is dependent on timing behavior of the first circuit; and a second circuit including a second plurality of components, the second circuit adapted to perform a different function that is dependent on different timing behavior of the second circuit, wherein a first geometry of a first layout of the first circuit is substantially the same as a second geometry of a second layout of the second circuit.

11 . The chip of claim 10 , wherein the first plurality of components includes one or more first components that are substantially the same as one or more second components of the second plurality of components, the one or more first components being in first positions in the first circuit that correspond to second positions of the one or more second components in the second circuit.

12 . The chip of claim 10 , wherein the first plurality of components and the second plurality of components include components in corresponding positions of the first and second circuit that have substantially the same geometries but different timing behaviors.

13 . The chip of claim 10 , wherein the first plurality of components includes at least one component selected from a pool of components characterized by substantially the same geometries but varied timing behaviors, the at least one component characterized by timing behavior suitable for implementing the timing behavior of the first circuit.

14 . The chip of claim 13 , wherein the first plurality of components includes at least one other component selected from the pool, the at least one other component characterized by other timing behavior suitable for implementing the timing behavior of the first circuit, and wherein a quantity and a positioning of said at least one component and said at least one other component are suitable for implementing the timing behavior of the first circuit.

15 . The chip of claim 10 , wherein the second plurality of components includes at least one component selected from a pool of components characterized by substantially the same geometries but varied component timing behaviors, the at least one component characterized by timing behavior suitable for implementing the different timing behavior of the second circuit.

16 . The chip of claim 15 , wherein the second plurality of components includes at least one other component selected from the pool, the at least one other component characterized by other timing behavior suitable for implementing the different timing behavior of the second circuit.

17 . The chip of claim 16 , wherein a quantity and a positioning of said at least one component and said at least one other component are suitable for implementing the different timing behavior of the second circuit.

18 . The circuit of claim 10 , wherein one of: the function and the different function is a buffer function, and another one of: the function and the different function is an inverter function.

19 . The chip of claim 10 , including at least one of: a plurality of the first circuit or a plurality of the second circuit.

20 . A method for generating at least one new netlist for a chip, the at least one new netlist being a modified version of at least one old netlist for the chip, the method comprising:
editing the at least one old netlist, the editing including: integrating representations for a plurality of circuits into the at least one old netlist, the representations comprising at least one of: at least one replacement representation replacing at least one existing representation that was included in the at least one old netlist, or at least one additional representation not replacing any existing representation that was included in the at least one old netlist,
wherein the plurality of circuits are each adapted to perform one of a plurality of different functions respectively dependent on a plurality of different timing behaviors, and
wherein a plurality of geometries of a plurality of layouts for the plurality of circuits are substantially the same.

Assignees

• Cisco Tech Inc

Inventors

• Darmon David
• Klein Avi
• Salmon Yehuda
• Grabovsky Aharon
• Attia Ruben

Classifications

• H10W42/405 Primary

  using active circuits · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title