Predicting data correlation using multivalued logical outputs in static random access memory (sram) storage cells

Patent metadata

Field	Value
Publication number	US-2018240512-A1
Application number	US-201815892037-A
Country	US
Kind code	A1
Filing date	Feb 8, 2018
Priority date	Feb 21, 2017
Publication date	Aug 23, 2018
Grant date	—

Abstract

Predicting data correlation using multivalued logical outputs in SRAM storage cells including generating a plurality of logical outputs for each of a plurality of variable sets, wherein each variable in each variable set is a data point, and wherein each logical output is a binary indication of a relationship between the data points; writing, into storage cells, each logical output of the plurality of logical outputs for each of the plurality of variable sets; and for each group of corresponding logical outputs of the plurality of logical outputs: activating a fight port for the storage cells storing corresponding logical outputs, wherein activating the fight port causes each corresponding logical output to adjust a resulting voltage based on the logical output stored in each storage cell; and measuring the resulting voltage on a bitline of the activated fight port to determine a correlation probability for the corresponding logical outputs.

First claim

1 . A method of predicting data correlation using multivalued logical outputs in modified static random access memory (SRAM) storage cells comprising:
writing, into modified SRAM storage cells, a plurality of logical outputs for each of a plurality of variable sets, wherein each variable in each variable set is a data point, and wherein each logical output is a binary indication of a relationship between the data points of each variable set; and for each group of corresponding logical outputs of the plurality of logical outputs: activating a fight port for the modified SRAM storage cells storing corresponding logical outputs, wherein activating the fight port causes each corresponding logical output to adjust a resulting voltage based on the logical output stored in each modified SRAM storage cell, wherein the resulting voltage on a bitline of the activated fight port determines a correlation probability for the corresponding logical outputs.

2 . The method of claim 1 , wherein measuring the resulting voltage on the bitline of the activated fight port to determine a correlation probability for the corresponding logical outputs comprises:
transferring the resulting voltage to a sense amp; and generating, by the sense amp, a correlation probability signal by comparing the resulting voltage to a voltage threshold.

3 . The method of claim 2 , wherein the correlation probability signal indicates a confidence level for the correlation probability.

4 . The method of claim 1 , wherein the each of the logical outputs are generated by applying a different logic operation to each of the plurality of variable sets.

5 . The method of claim 1 , wherein the fight port activates a plurality of storage cells on a bitline of the modified SRAM, and wherein the resulting voltage is applied to the bitline of the fight port.

6 . The method of claim 1 , wherein writing, into modified SRAM cells, each logical output of the plurality of logical outputs for each of the plurality of variable sets comprises:
writing each of the plurality of logical outputs for each variable set on a different modified SRAM storage cell along the same wordline of the modified SRAM.

7 . The method of claim 1 , wherein the fight port is operatively coupled to a group of modified SRAM storage cells on different wordlines.

8 . An apparatus for predicting data correlation using multivalued logical outputs in modified static random access memory (SRAM) storage cells, the apparatus configured to carry out the steps of:
writing, into modified SRAM storage cells, a plurality of logical outputs for each of a plurality of variable sets, wherein each variable in each variable set is a data point, and wherein each logical output is a binary indication of a relationship between the data points of each variable set; and for each group of corresponding logical outputs of the plurality of logical outputs: activating a fight port for the modified SRAM storage cells storing corresponding logical outputs, wherein activating the fight port causes each corresponding logical output to adjust a resulting voltage based on the logical output stored in each modified SRAM storage cell, wherein the resulting voltage on a bitline of the activated fight port determines a correlation probability for the corresponding logical outputs.

9 . The apparatus of claim 8 , wherein measuring the resulting voltage on a bitline of the activated fight port to determine a correlation probability for the corresponding logical outputs comprises:
transferring the resulting voltage to a sense amp; and generating, by the sense amp, a correlation probability signal by comparing the resulting voltage to a voltage threshold.

10 . The apparatus of claim 9 , wherein the correlation probability signal indicates a confidence level for the correlation probability.

11 . The apparatus of claim 8 , wherein the each of the logical outputs are generated by applying a different logic operation to each of the plurality of variable sets.

12 . The apparatus of claim 8 , wherein the fight port activates a plurality of storage cells on a bitline of the modified SRAM, and wherein the resulting voltage is applied to the bitline of the fight port.

13 . The apparatus of claim 8 , wherein writing, into modified SRAM cells, each logical output of the plurality of logical outputs for each of the plurality of variable sets comprises:
writing each of the plurality of logical outputs for each variable set on a different modified SRAM storage cell along the same wordline of the modified SRAM.

14 . The apparatus of claim 8 , wherein the fight port is operatively coupled to a group of modified SRAM storage cells on different wordlines.

15 . A computer program product for predicting data correlation using multivalued logical outputs in modified static random access memory (SRAM) storage cells, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:
writing, into modified SRAM storage cells, a plurality of logical outputs for each of a plurality of variable sets, wherein each variable in each variable set is a data point, and wherein each logical output is a binary indication of a relationship between the data points of each variable set; and for each group of corresponding logical outputs of the plurality of logical outputs: activating a fight port for the modified SRAM storage cells storing corresponding logical outputs, wherein activating the fight port causes each corresponding logical output to adjust a resulting voltage based on the logical output stored in each modified SRAM storage cell, wherein the resulting voltage on a bitline of the activated fight port determines a correlation probability for the corresponding logical outputs.

16 . The computer program product of claim 15 , wherein measuring the resulting voltage on a bitline of the activated fight port to determine a correlation probability for the corresponding logical outputs comprises:
transferring the resulting voltage to a sense amp; and generating, by the sense amp, a correlation probability signal by comparing the resulting voltage to a voltage threshold.

17 . The computer program product of claim 16 , wherein the correlation probability signal indicates a confidence level for the correlation probability.

18 . The computer program product of claim 15 , wherein the each of the logical outputs are generated by applying a different logic operation to each of the plurality of variable sets.

19 . The computer program product of claim 15 , wherein the fight port activates a plurality of storage cells on a bitline of the modified SRAM, and wherein the resulting voltage is applied to the bitline of the fight port.

20 . The computer program product of claim 15 , wherein writing, into modified SRAM cells, each logical output of the plurality of logical outputs for each of the plurality of variable sets comprises:
writing each of the plurality of logical outputs for each variable set on a different modified SRAM storage cell along the same wordline of the modified SRAM.

Assignees

• IBM

Inventors

• Erickson Karl R
• Paone Phil C
• Paulsen David P
• Sheets Ii John E
• Uhlmann Gregory J

Classifications

• G11C11/418

  Address circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C2029/5004

  Voltage · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title