Memory partitioning for a computing system with memory pools

Patent metadata

Field	Value
Publication number	US-2018239709-A1
Application number	US-201715440242-A
Country	US
Kind code	A1
Filing date	Feb 23, 2017
Priority date	Feb 23, 2017
Publication date	Aug 23, 2018
Grant date	—

Abstract

A computing system comprises at least one processing unit, at least one memory controller in communication with the processing unit, and a main memory in communication with the processing unit through the memory controller. A memory hierarchy of the computing system includes at least one cache, the memory controller, and the main memory. The memory hierarchy is divided into a plurality of memory pools. The main memory comprises a set of memory modules split in ranks each having a rank address defined by a set of rank address bits. Each rank has a set of memory devices comprising one or more banks each having a bank address defined by a set of bank address bits. A plurality of threads execute on the processing unit, and are assigned to the memory pools based on one or more memory partitioning techniques, including bank partitioning, rank partitioning, or memory controller partitioning.

First claim

What is claimed is:

1 . A computing system, comprising:
at least one processing unit; at least one memory controller in operative communication with the at least one processing unit, with or without cache; and a main memory in operative communication with the at least one processing unit through the at least one memory controller; wherein a memory hierarchy of the computing system includes at least one cache, the at least one memory controller, and the main memory, wherein the memory hierarchy is divided into a plurality of memory pools; wherein the main memory comprises a set of memory modules split in ranks each having a rank address defined by a set of rank address bits, and each rank having a set of memory devices, each of the memory devices comprising one or more banks each having a bank address defined by a set of bank address bits; wherein a plurality of threads execute on the at least one processing unit and are assigned to the memory pools based on one or more memory partitioning techniques comprising:
bank partitioning, which uses the bank address bits to define a size and pattern of one or more of the memory pools;
rank partitioning, which uses the rank address bits to access the one or more ranks; or
memory controller partitioning, which uses memory controller interleaving.

2 . The computing system of claim 1 , wherein the main memory comprise Dynamic Random Access Memory (DRAM).

3 . The computing system of claim 1 , wherein the threads are also assigned to the memory pools based on a cache partitioning technique, which uses cache index address bits to define a size and number of cache partitions.

4 . The computing system of claim 1 , wherein at least some of the threads are assigned to the same memory pool.

5 . The computing system of claim 1 , wherein at least some of the threads are respectively assigned to different memory pools.

6 . The computing system of claim 1 , wherein the at least one processing unit comprises one or more Central Processing Unit (CPU) cores.

7 . The computing system of claim 6 , wherein at least some of the threads are mapped onto the same CPU core.

8 . The computing system of claim 6 , wherein at least some of the threads are respectively mapped onto different CPU cores.

9 . The computing system of claim 1 , wherein at least some of the memory pools are respectively mapped, in a one to one (1:1) correspondence, to the at least one memory controller, the one or more ranks, or the one or more banks.

10 . The computing system of claim 1 , wherein at least some of the memory pools are respectively mapped, in a one to many (1:N) correspondence, to multiples of the at least one memory controller, the one or more ranks, and the one or more banks.

11 . An avionics computer system, comprising:
a multi-core processor unit, comprising:
one or more processor clusters, each of which comprise a plurality of central Central Processing Unit (CPU) cores, each of the cores having a private level first cache and a shared level second cache;
an interconnect operatively coupled to the one or more processor clusters; and
one or more memory controllers in operative communication with the one or more processor clusters through the interconnect;
a main memory in operative communication with the one or more processor clusters through the one or more memory controllers, wherein a memory hierarchy of the avionics computer system includes at least one of the first or second caches, the one or more memory controllers, and the main memory, wherein the memory hierarchy is divided into a plurality of memory pools; wherein the main memory comprises a set of Dual In-line Memory Modules (DIMMs) split in ranks each having a rank address defined by a set of rank address bits, and each rank having a set of Dynamic Random Access Memory (DRAM) devices, each of the DRAM devices comprising one or more banks each having a bank address defined by a set of bank address bits; wherein a plurality of threads execute on the CPU cores, wherein the threads are assigned to the memory pools based on one or more memory partitioning techniques comprising:
bank partitioning, which uses the bank address bits to define a size and pattern of one or more of the memory pools;
rank partitioning, which uses the rank address bits to access the one or more ranks; or
memory controller partitioning, which uses memory controller interleaving to either fairly distribute the memory requests to multiple memory controllers or completely isolate the memory requests to a particular memory controller;
wherein the avionics computer system is implemented as part of an avionics platform onboard an aircraft.

12 . The avionics computer system of claim 11 , wherein one or more of the threads are also assigned to one or more of the memory pools based on a cache partitioning technique, which uses cache index address bits to define a size and number of cache partitions.

13 . The avionics computer system of claim 11 , wherein at least some of the threads are assigned to the same memory pool.

14 . The avionics computer system of claim 11 , wherein at least some of the threads are respectively assigned to different memory pools.

15 . The avionics computer system of claim 11 , wherein at least some of the threads are mapped onto the same CPU core.

16 . The avionics computer system of claim 11 , wherein at least some of the threads are respectively mapped onto different CPU cores.

17 . The avionics computer system of claim 11 , wherein at least some of the memory pools are respectively mapped, in a one to one (1:1) correspondence, to the one or more memory controllers, the one or more ranks, or the one or more banks.

18 . The avionics computer system of claim 11 , wherein at least some of the memory pools are respectively mapped, in a one to many (1:N) correspondence, to multiples of the one or more memory controllers, the one or more ranks, and the one or more banks.

19 . A method of operating a computing system, the method comprising:
dividing a memory hierarchy of the computing system into a plurality of memory pools, the memory hierarchy including at least one cache, at least one memory controller, and a main memory;
wherein the main memory comprises a set of memory modules split in ranks each having a rank address defined by a set of rank address bits, and each rank having a set of memory devices, each of the memory devices comprising one or more banks each having a bank address defined by a set of bank address bits; and
assigning each of a plurality of threads, which execute on at least one processing unit in the computing system, to one or more of the memory pools based on one or more memory partitioning techniques comprising:
bank partitioning, which uses the bank address bits to define a size and pattern of one or more of the memory pools;
rank partitioning, which uses the rank address bits to access the one or more ranks; or
memory controller partitioning, which uses memory controller interleaving to either fairly distribute the memory requests to multiple memory controllers or completely isolate the memory requests to a particular memory controller.

20 . The method of claim 19 , wherein one or more of the threads are also assigned to one or more of the memory pools based on a cache partitioning technique, which uses cache index address bits to define a size and number of cache partitions.

Assignees

• Honeywell Int Inc

Inventors

• Zaykov Pavel
• Matusova Lucie

Classifications

• G06F2212/173

  Vehicle or other transportation · CPC title

• G06F12/0851

  Cache with interleaved addressing · CPC title

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title