Method and device for recording memory access operation information

Patent metadata

Field	Value
Publication number	US-2018239558-A1
Application number	US-201815895145-A
Country	US
Kind code	A1
Filing date	Feb 13, 2018
Priority date	Feb 20, 2017
Publication date	Aug 23, 2018
Grant date	—

Abstract

A method and a device for recording memory access operation information are provided by the present disclosure. The method comprises: recording memory access operations between a processor and a memory during a target running process to form an memory access sequence information of the target running process, wherein each of the memory access operation information in the memory access sequence information includes a memory access type, a memory access address and a memory access data; and determining a final storage state of the memory during the target running process according to the memory access sequence information of the target running process. According to the embodiments of the present disclosure, the final storage state of the memory during the target running process may be obtained by using less storage resources, and the hardware overhead is reduced.

First claim

What is claimed is:

1 . A method for recording memory access operation information, comprising:
recording memory access operations between a processor and a memory during a target running process to form a memory access sequence information of the target running process, wherein each of the memory access operation information in the memory access sequence information includes a memory access type, a memory access address and a memory access data; and determining a final storage state of the memory during the target running process according to the memory access sequence information of the target running process.

2 . The method according to claim 1 , wherein determining the final storage state of the memory during the target running process according to the memory access sequence information of the target running process comprises:
obtaining a first memory access operation information in the memory access sequence information; writing the first memory access operation information into a first buffer when the memory access type of the first memory access operation information is a write operation; and obtaining the final storage state from the first buffer.

3 . The method according to claim 2 , wherein writing the first memory access operation information into the first buffer when the memory access type of the first memory access operation information is a write operation comprises:
determining whether the memory access address of the first memory access operation information is already recorded in the first buffer; writing the first memory access operation information into the first buffer to overwrite a previous memory access operation information when the memory access address of the first memory access operation information is already recorded in the first buffer; and inserting the first memory access operation information into the first buffer when the memory access address of the first memory access operation information is not recorded in the first buffer,

4 . The method according to claim 2 , further comprising:
obtaining the memory access operation information corresponding to a first-time read operation during the target running process from the memory access sequence information; and taking the memory access data in the memory access operation information corresponding to the first-time read operation as an input information or an initial running state of a checking device such that the checking device executes a task of the target running process in a manner conforming to a predefined behavior, wherein the predefined behavior is a hardware behavior standard of the processor.

5 . The method according to claim 3 , further comprising:
obtaining the memory access operation information corresponding to a first-time read operation during the target running process from the memory access sequence information; and taking the memory access data in the memory access operation information corresponding to the first-time read operation as an input information or an initial running state of a checking device such that the checking device executes a task of the target running process in a manner conforming to a predefined behavior, wherein the predefined behavior is a hardware behavior standard of the processor.

6 . The method according to claim 4 , wherein obtaining the memory access operation information corresponding to a first-time read operation during the target running process from the memory access sequence information comprises:
obtaining a second memory access operation information in the memory access sequence information; writing the second memory access operation information into a second buffer when the memory access type of the second memory access operation information is a read operation; and obtaining the memory access operation information corresponding to the first-time read operation from the second buffer.

7 . The method according to claim 6 , further comprising:
determining whether a memory access address of the second memory access operation information is already recorded in the first buffer when the memory access type of the second memory access operation information is a read operation; writing the second memory access operation information into the first buffer when the memory access address of the second memory access operation information is not recorded in the first buffer; writing an output data of the checking device into the second buffer when the checking device executes the task of the target running process; and sequentially traversing and comparing the memory access data and the memory access type corresponding to a same memory access address in the second buffer and the first buffer to determine whether the processor is secure.

8 . The method according to claim 6 , further comprising:
writing an output data of the checking device into the second buffer when the checking device executes the task of the target running process; determining whether a memory access address of the output data is already recorded in the first buffer; and determining whether the processor is secure according to the final storage state of the memory during the target running process when the memory access address of the output data is already recorded in the first buffer.

9 . The method according to claim 8 , wherein determining whether the processor is secure according to the final storage state of the memory during the target running process comprises:
traversing the memory access operation information in the first buffer to determine whether a same memory access data corresponding to a same memory access address is already recorded in the second buffer; determining that the processor is secure when the same memory access data corresponding to the same memory access address is already recorded in the second buffer; and determining that the processor is not secure when the same memory access data corresponding to the same memory access address is not recorded in the second buffer.

10 . The method according to claim 1 , wherein before recording the memory access operations between the processor and the memory during the target running process, the method further comprises:
obtaining an address range to be checked; and selecting the memory access operation to be recorded during the target running process according to the address range to be checked.

11 . A device for recording memory access operation information, comprising:
a memory access operation recording unit, configured to record memory access operations between a processor and a memory during a target running process to form an memory access sequence information of the target running process, wherein each of the memory access operation information in the memory access sequence information includes a memory access type, a memory access address and a memory access data; and a data organization unit, configured to determine a final storage state of the memory during the target running process according to the memory access sequence information of the target running process.

12 . The device according to claim 11 , wherein the data organization unit comprises: a first memory access operation information obtaining module, a first processing module, a first buffer, and a final storage state obtaining module; wherein
the first memory access operation information obtaining module is configured to obtain a first memory access operation information in the memory access sequence information; the first processing module is configured to write the first memory access operation information into the first buffer when the memory access type of the first memory acce

Assignees

• Univ Tsinghua

Inventors

• Liu Leibo
• Luo Ao
• Wei Shaojun

Classifications

• G06F3/0622

  in relation to access · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title