Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
US2018233584A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018233584-A1 |
| Application number | US-201815947969-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 9, 2018 |
| Priority date | Oct 8, 2015 |
| Publication date | Aug 16, 2018 |
| Grant date | — |
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A method of fabricating a thin film transistor includes preparing a plastic substrate, forming a transparent active layer on the plastic substrate through an atomic layer deposition method by providing a first source including zinc on the plastic substrate and providing a second source including sulfur on the plastic substrate, providing a gate electrode overlapping with the transparent active layer, and providing a gate insulating layer between the gate electrode and the transparent active layer. A ratio of the providing of the first source to the providing of the second source ranges from 7:1 to 13:1.
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What is claimed is: 1 . A method of fabricating a thin film transistor, the method comprising: preparing a plastic substrate; forming a transparent active layer on the plastic substrate through an atomic layer deposition method by providing a first source including zinc on the plastic substrate and providing a second source including sulfur on the plastic substrate, wherein a ratio of the providing of the first source to the providing of the second source ranges from 7:1 to 13:1; providing a gate electrode overlapping with the transparent active layer; and providing a gate insulating layer between the gate electrode and the transparent active layer. 2 . The method of claim 1 , wherein the first source and the second source are provided at a process temperature of 80 degrees Celsius. 3 . The method of claim 1 , wherein flexibility of the transparent active layer is adjusted by adjusting the number of times the first source and the second source are provided, under the condition that the ratio of the providing of the first source to the providing of the second source ranges from 7:1 to 13:1. 4 . The method of claim 3 , wherein the flexibility of the transparent active layer increases as a ratio of the providing of the second source to the providing of the first source increases. 5 . The method of claim 1 , wherein the second source has a thiol group. 6 . A thin film transistor comprising: a plastic substrate; a transparent active layer disposed on the plastic substrate and including sulfur of 2.60% to 6.45% and zinc of 33.98% to 43.90%; a gate electrode overlapping with the transparent active layer; and a gate insulating layer between the gate electrode and the transparent active layer. 7 . The thin film transistor of claim 6 , wherein the thin film transistor has an on/off ratio of 10 6 or more. 8 . The thin film transistor of claim 6 , wherein the transparent active layer has a mobility of 7 cm 2 /Vs or more.
Sulfides · CPC title
being insulating materials · CPC title
being non-crystalline insulating materials, e.g. glass or polymers · CPC title
using chemical vapour deposition [CVD] · CPC title
Electricity · mapped topic
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