Semiconductor Structure and Method

Patent metadata

Field	Value
Publication number	US-2018204902-A1
Application number	US-201715582963-A
Country	US
Kind code	A1
Filing date	May 1, 2017
Priority date	Jan 13, 2017
Publication date	Jul 19, 2018
Grant date	—

Abstract

A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

First claim

1 . A method of manufacturing a semiconductor device, the method comprising:
forming a first cobalt-zirconium-tantalum (CZT) layer and a second CZT layer over a semiconductor substrate, wherein the first CZT layer comprises:
a first metal layer;
a first CZT material; and
a first oxidized CZT (OCZT) material;
applying a mask over the second CZT layer; wet etching the second CZT layer to expose a portion of the first CZT layer; treating the exposed portion of the first CZT layer; forming a first dielectric material over the second CZT layer; forming a first inductor coil over the first dielectric material; forming a second dielectric material over the first inductor coil; and forming a third CZT layer through the second dielectric material and in contact with the second CZT layer.

2 . The method of claim 1 , wherein the first metal layer comprises tantalum.

3 . The method of claim 1 , wherein the wet etching forms a stairstep pattern.

4 . The method of claim 3 , wherein the stairstep pattern has an angle of between 5 degrees and 70 degrees.

5 . The method of claim 1 , further comprising forming a third dielectric material after the forming the first dielectric material and prior to forming the firsts inductor coil.

6 . The method of claim 5 , wherein the first dielectric material is silicon nitride and the third dielectric material is silicon oxide.

7 . The method of claim 1 , wherein the treating is performed at least in part with a plasma process.

8 . A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of cobalt-zirconium-tantalum (CZT) layers over a substrate, wherein each one of the plurality of CZT layers comprises:
a metal layer;
an oxidized CZT material layer; and
a CZT material between the metal layer and the oxidized CZT material layer;
shaping the plurality of CZT layers into a stairstep pattern; depositing a first dielectric cap over the stairstep pattern; depositing a second dielectric cap over the first dielectric cap; forming an inductor coil over the second dielectric cap; depositing a third dielectric cap over the inductor coil; forming openings to expose the plurality of CZT layers; depositing a capping CZT layer over the inductor coil and through the openings.

9 . The method of claim 8 , wherein the first dielectric cap comprises a first material and the third dielectric cap comprises the first material.

10 . The method of claim 9 , wherein the second dielectric cap comprises a second material different from the first material.

11 . The method of claim 10 , wherein the first material is silicon oxide and the second material is silicon nitride.

12 . The method of claim 10 , wherein the first material is silicon nitride and the second material is silicon oxide.

13 . The method of claim 8 , further comprising treating the plurality of CZT layers prior to depositing the first dielectric cap.

14 . The method of claim 8 , wherein the shaping the plurality of CZT layers is performed at least in part with a wet etching process.

15 .- 20 . (canceled)

21 . A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of layers over a semiconductor substrate, wherein the plurality of layers has a stairstep sidewall and the forming the plurality of layers comprises:
forming a metal layer;
forming a cobalt-zirconium-tantalum (CZT) material over the metal layer; and
forming an oxidized CZT material over the CZT material;
forming a plurality of dielectric layers over the plurality of layers; forming an inductor coil over the plurality of dielectric layers; forming a capping dielectric over the inductor coil; and forming a second CZT material which extends over the capping dielectric, through the plurality of dielectric layers, and is in contact with at least one of the plurality of layers.

22 . The method of claim 21 , wherein the stairstep sidewall has an angle of between about 5 degrees and about 70 degrees.

23 . The method of claim 21 , wherein the forming the metal layer comprises forming tantalum.

24 . The method of claim 21 , wherein the stairstep sidewall has a step length of between about 0.25 μm and about 2 μm.

25 . The method of claim 21 , wherein the stairstep sidewall has a step height of between about 0.1 μm and about 0.7 μm.

26 . The method of claim 21 , wherein after the forming the second CZT material the second CZT material extends through a first opening, the first opening extending through the capping dielectric and the plurality of dielectric layers, wherein the first opening has a first sidewall with a kink profile.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Wei-Li
• Chen Chi-Cheng
• Huang Hon-Lin
• Chou Chien-Chih
• Ku Chin-Yu
• Chen Chen-Shien

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/269

  pre- or post-treatments, e.g. anti-corrosion processes · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W44/501 Primary

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title