Memory device

Patent metadata

Field	Value
Publication number	US-2018204615-A1
Application number	US-201815920531-A
Country	US
Kind code	A1
Filing date	Mar 14, 2018
Priority date	Mar 7, 2014
Publication date	Jul 19, 2018
Grant date	—

Abstract

A memory device includes a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node; a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node. The input value at the second input node of the sense amplifier is changed such that a change amount of the input value between two different temperatures T2 and (T2+ΔT) in a second temperature region, at a temperature higher than in a first temperature region, of the memory cell becomes larger than the change amount of the input value between two different temperatures T1 and (T1+ΔT) in the first temperature region of the memory cell, where ΔT is an increase amount of the temperature.

First claim

What is claimed is:

1 . (canceled)

2 . A memory device comprising:
a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node; a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node, wherein a reference current generation circuit provided with a replica circuit is connected to the second input node of the sense amplifier.

3 . The memory device according to claim 2 , wherein the replica circuit comprises a replica of the memory cell.

4 . The memory device according to claim 2 , wherein the memory cell comprises a memory element and a cell transistor, and the replica circuit comprises a replica of the memory element and a replica of the cell transistor.

5 . The memory device according to claim 4 , wherein the replica of the memory element has a same structure as the memory element and the replica of the cell transistor has a same structure as the cell transistor.

6 . The memory device according to claim 5 , wherein the memory element and the replica of the memory element include resistance change memory elements.

7 . The memory device according to claim 5 , wherein the cell transistor and the replica of the cell transistor include MOSFETs.

8 . The memory device according to claim 2 , wherein the first path comprises a column switch connected electrically the memory cell, and the replica circuit comprises a replica of the column switch.

9 . The memory device according to claim 8 , wherein the replica of the column switch has a same structure as the column switch.

10 . The memory device according to claim 9 , wherein the column switch and the replica of the column switch include MOSFETs.

11 . The memory device according to claim 2 , wherein the replica circuit comprises a first transistor connected electrically the reference current generation circuit and a second transistor connected electrically the first transistor, and the first transistor and the second transistor provide a current mirror circuit.

12 . The memory device according to claim 11 , wherein the replica circuit comprises a replica of the memory cell, and
wherein the second transistor and the replica of the memory cell are connected electrically in series between a power supply node and the ground node.

13 . The memory device according to claim 11 , wherein the first path comprises a column switch connected electrically the memory cell, and the replica circuit comprises a replica of the column switch, and
wherein the second transistor and the replica of the column switch are connected electrically in series between a power supply node and the ground node.

Assignees

• Toshiba Memory Corp

Inventors

• Katayama Akira

Classifications

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title