Approximation of resistor-capacitor circuit extraction for thread-safe design changes

Patent metadata

Field	Value
Publication number	US-2018203969-A1
Application number	US-201715408856-A
Country	US
Kind code	A1
Filing date	Jan 18, 2017
Priority date	Jan 18, 2017
Publication date	Jul 19, 2018
Grant date	—

Abstract

A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.

First claim

What is claimed is:

1 . A method of fabricating an integrated circuit, the method comprising:
performing, using a processor, a design change for a net among a plurality of nets of the integrated circuit; performing, using the processor, an extraction for the net, the performing the extraction including re-computing values for a resistor-capacitor (RC) circuit representation of the net; recording re-computed values resulting from the re-computing and a timestamp of the extraction; changing a capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net; updating timing and noise parameters for the net and the neighboring net to updated timing and noise parameters; performing timing analysis based on the updated timing and noise parameters; and implementing a physical implementation of the integrated circuit based on a result of the timing analysis meeting design criteria.

2 . The method according to claim 1 , further comprising determining the design change based on a previous iteration of the timing analysis.

3 . The method according to claim 1 , wherein the performing the design change and performing the extraction is for two or more nets using two or more of the processors in a multi-threaded arrangement.

4 . The method according to claim 3 , wherein the changing the capacitance value is performed for all the neighboring nets of all the two or more nets that undergo the design change after the performing the extraction is completed for all the two or more nets.

5 . The method according to claim 4 , wherein the changing the capacitance value of the capacitor coupling one of the two or more nets with a corresponding neighboring net is based on a most recent change to the capacitance value based on more than one of the extractions affecting the capacitance value.

6 . The method according to claim 5 , wherein the changing the capacitance value based on the most recent change is based on the timestamp associated with the most recent extraction that re-computed the capacitance value.

7 . The method according to claim 3 , wherein the performing the design change and the extraction is done iteratively for each thread in the multi-threaded arrangement.

8 . A system to design an integrated circuit, the system comprising:
a memory device configured to store a resistor-capacitor (RC) circuit representation of a plurality of nets associated with the integrated circuit; a processor associated with one net among the plurality of nets, the processor configured to perform a design change for the one net among the plurality of nets, perform an extraction for the one net, the extraction including re-computation of values for the RC circuit representation of the one net, and record re-computed values resulting from the re-computation with a timestamp for the extraction; and a second processor associated with a neighboring net of the one net, the second processor configured to change a capacitance value of a capacitor coupling the one net with the neighboring net in the RC circuit representation of the neighboring net to be the capacitance value of the capacitor coupling the one net with the neighboring net that was re-computed for the RC circuit representation of the one net.

9 . The system according to claim 8 , wherein the processor and the second processor are a same processor.

10 . The system according to claim 8 , wherein the processor and the second processor operate in a multi-threaded arrangement.

11 . The system according to claim 10 , wherein the processor and the second processor perform the design change and the extraction for two or more nets in parallel.

12 . The system according to claim 11 , wherein the processor and the second processor change the capacitance value for all the neighboring nets of the two or more nets after performing the extraction for the two or more nets.

13 . The system according to claim 12 , wherein the processor and the second processor change the capacitance value based on the most recent extraction that affects the capacitance value according to the timestamp associated with each extraction.

14 . The system according to claim 10 , wherein the processor and the second processor perform the design change and the extraction iteratively.

15 . A computer program product for performing design of an integrated circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to perform a method comprising:
performing a design change for a net among a plurality of nets of the integrated circuit; performing an extraction for the net, the performing the extraction including re-computing values for a resistor-capacitor (RC) circuit representation of the net; recording re-computed values resulting from the re-computing and a timestamp of the extraction; changing a capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net; updating timing and noise parameters for the net and the neighboring net to updated timing and noise parameters; and performing timing analysis based on the updated timing and noise parameters.

16 . The computer program product according to claim 15 , wherein the determining the design change is based on a previous iteration of the timing analysis.

17 . The computer program product according to claim 15 , wherein the performing the design change and performing the extraction is for two or more nets using two or more of the processors in a multi-threaded arrangement.

18 . The computer program product according to claim 17 , wherein the changing the capacitance value is performed for all the neighboring nets of all the two or more nets that undergo the design change after the performing the extraction is completed for all the two or more nets.

19 . The computer program product according to claim 18 , wherein the changing the capacitance value of the capacitor coupling one of the two or more nets with a corresponding neighboring net is based on a most recent change to the capacitance value based on more than one of the extractions affecting the capacitance value.

20 . The computer program product according to claim 19 , wherein the changing the capacitance value based on the most recent change is based on the timestamp associated with the most recent extraction that re-computed the capacitance value.

Assignees

• IBM

Inventors

• Ko Tsz-Mei
• Morsey Jason D
• Washburn Steven E
• Williams Patrick M

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F2119/10

  Noise analysis or noise optimisation · CPC title