Interconnect structure and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-2018197819-A1
Application number	US-201715400600-A
Country	US
Kind code	A1
Filing date	Jan 6, 2017
Priority date	Jan 6, 2017
Publication date	Jul 12, 2018
Grant date	—

Abstract

An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.

First claim

1 . An interconnect structure, comprising:
a substrate; at least one ultra-thick metal (UTM) layer disposed on the substrate; a first dielectric layer disposed on the at least one UTM layer and exposing the at least one UTM layer, wherein a stress of the first dielectric layer is larger than or equal to −500 Mpa, and less than −301 Mpa; and at least one pad metal layer disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.

2 . The interconnect structure of claim 1 , wherein a material of the first dielectric layer comprises silicon oxide.

3 . The interconnect structure of claim 1 , further comprising a blocking layer disposed between the first dielectric layer and the at least one UTM layer.

4 . The interconnect structure of claim 3 , wherein a material of the blocking layer comprises silicon nitride.

5 . The interconnect structure of claim 1 , wherein the number of the at least one UTM layer is plural, and the number of the at least one pad metal layer is plural.

6 . The interconnect structure of claim 5 , further comprising a second dielectric layer disposed between the UTM layers.

7 . The interconnect structure of claim 5 , further comprising a passivation layer structure disposed on a surface of an opening between the pad metal layers, wherein the passivation layer structure comprises:
a first passivation layer disposed on the surface of the opening between the pad metal layers; and a second passivation layer disposed on the first passivation layer.

8 . The interconnect structure of claim 7 , wherein the passivation layer structure further extends on a portion of the pad metal layers.

9 . The interconnect structure of claim 7 , wherein a stress of the first passivation layer is −50 Mpa to −200 Mpa.

10 . The interconnect structure of claim 7 , wherein a material of the first passivation layer comprises high density plasma-chemical vapor deposition (HDP-CVD) oxide.

11 . The interconnect structure of claim 7 , wherein a material of the second passivation layer comprises silicon nitride.

12 . A method of fabricating an interconnect structure, comprising:
forming at least one UTM layer on a substrate; forming a first dielectric layer on the at least one UTM layer, wherein the first dielectric layer exposes the at least one UTM layer, and a stress of the first dielectric layer is larger than or equal to −500 Mpa, and less than −301 Mpa; and forming at least one pad metal layer on the first dielectric layer, wherein the at least one pad metal layer is electrically connected to the at least one UTM layer exposed by the first dielectric layer.

13 . The method of fabricating the interconnect structure of claim 12 , wherein a method of forming the at least one UTM layer comprises a damascene method.

14 . The method of fabricating the interconnect structure of claim 12 , wherein a method of forming the first dielectric layer comprises a plasma-enhanced chemical vapor deposition (PECVD) method.

15 . The method of fabricating the interconnect structure of claim 12 , wherein a method of forming the at least one pad metal layer comprises a combination of a deposition process, a lithography process, and an etching process.

16 . The method of fabricating the interconnect structure of claim 12 , wherein the number of the at least one UTM layer is plural, and the number of the at least one pad metal layer is plural.

17 . The method of fabricating the interconnect structure of claim 16 , further comprising forming a second dielectric layer between the UTM layers.

18 . The method of fabricating the interconnect structure of claim 16 , further comprising forming a passivation layer structure on a surface of an opening between the pad metal layers, wherein the passivation layer structure comprises:
a first passivation layer disposed on the surface of the opening between the pad metal layers; and a second passivation layer disposed on the first passivation layer.

19 . The method of fabricating the interconnect structure of claim 18 , wherein a method of forming the first passivation layer comprises a HDP-CVD method.

Assignees

• United Microelectronics Corp

Inventors

• Zhang keen
• Feng Ji
• Kong de-jin
• Li Yun-Fei
• Zhang guo-hai
• Tey Ching-Hwa
• Feng Jing

Classifications

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title