Method and apparatus to control a link power state

Patent metadata

Field	Value
Publication number	US-2018196488-A1
Application number	US-201815860300-A
Country	US
Kind code	A1
Filing date	Jan 2, 2018
Priority date	Dec 24, 2014
Publication date	Jul 12, 2018
Grant date	—

Abstract

A method is provided for controlling a link. This may include determining a condition of a first device coupled to the link, receiving, at the first device, a request for a specific link state from a second device coupled to the link, and determining a power state of the link based on the determined condition of the first device.

First claim

1 - 20 . (canceled)

21 . A non-transitory machine-readable medium comprising instructions that when executed cause one or more processors coupled to a link to perform operations to:
identify a condition of at least one component of the one or more processors or another device coupled to the link, wherein to identify the condition includes at least one of to identify a first power state of the at least one component and to identify a second power state of the at least one component, wherein the second power state is that is greater than the first power state; and in response to receipt of a request for a specific link state:
determine a first power state of the link based only on identification of the first power state of the at least one component; and
determine a second power state of the link based only on identification of the second power state of the at least one component, wherein the second power state of the link is greater than the first power state of the link.

22 . The non-transitory machine-readable medium of claim 21 , wherein the first power state of the link comprises a power save state.

23 . The non-transitory machine-readable medium of claim 22 , wherein the second power state of the link comprises a power on state.

24 . The non-transitory machine-readable medium of claim 21 , wherein the one or more processors or the another device coupled to the link comprises a first device and the request originates from a second device coupled to the link.

25 . The non-transitory machine-readable medium of claim 21 , wherein to identify the second power state of the at least one component includes to identify a predefined operation mode of the at least one component.

26 . The non-transitory machine-readable medium of claim 25 , wherein to identify the second power state of the link is based on the identified predefined operation mode of the at least one component.

27 . The non-transitory machine-readable medium of claim 25 , wherein the identified predefined operation mode of the at least one component comprises an active condition.

28 . The non-transitory machine-readable medium of claim 21 , wherein the link is a Peripheral Component Interconnect Express (PCIe) link.

29 . An electronic apparatus comprising:
first logic, at least a portion of which is hardware, to identify a condition of at least one component of a device, wherein the first logic to identify the condition includes at least one of the first logic to identify a first power state of the at least one component and the first logic to identify a second power state of the at least one component, wherein the second power state is greater than the first power state; and second logic, at least a portion of which is hardware, to determine a first power state of the link in response to a request for a specific link state, the second logic to determine the first power state of the link based only on identification of the first power state of the at least one component, the second logic to determine a second power state of the link in response to the request for the specific link state, the second logic to determine the second power state of the link based only on identification of the second power state of the at least one component, wherein the second power state of the link is greater than the first power state of the link.

30 . The electronic apparatus of claim 29 , wherein the first power state of the link comprises a power save state.

31 . The electronic apparatus of claim 30 , wherein the second power state of the link comprises a power on state.

32 . The electronic apparatus of claim 31 , wherein the first logic to identify the second power state of the at least one component comprises the first logic to identify an active condition of the at least one component.

33 . The electronic apparatus of claim 32 , wherein the second power state of the link is determined based on the identified active condition of the at least one component.

34 . The electronic apparatus of claim 29 , wherein the link is a Peripheral Component Interconnect Express (PCIe) link.

35 . The electronic apparatus of claim 29 , wherein the device comprises a Platform Controller Hub (PCH).

36 . The electronic apparatus of claim 29 , wherein the device comprises a chipset.

37 . The electronic apparatus of claim 29 , wherein the device comprises a Central Processor Unit (CPU).

38 . The electronic apparatus of claim 29 , wherein the device comprises a System on Chip (SoC) processor, and wherein the at least one component comprises an integrated component of the SoC processor.

39 . An apparatus, comprising:
a power supply; an upstream device coupled to one or more downstream devices via one or more links, respectively, the one or more links powered by the power supply; and a module to: identify a condition of at least one component of the upstream device, wherein identify the condition includes at least one of identify a first power state of the at least one component and identify a second power state of the at least one component, wherein the second power state is greater than the first power state; determine a power on state of a link of the one or more links in response to a request for a specific link state from a corresponding one of the one or more downstream devices, including determine the power on state of the link based only on identification of the first power state of the at least one component; and determine a power save state of the link of the one or more links in response to the request for the specific link state from the corresponding one of the one or more downstream devices, including determine the power save state of the link based only on identification of the second power state of the at least one component.

40 . The apparatus of claim 39 , wherein the upstream device comprises a processor, a platform controller hub, or a chipset.

Assignees

• Intel Corp

Inventors

• Gough Corey D
• Steiner Ian M
• Sistla Krishnakanth V

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3253

  Power saving in bus · CPC title