Thin film transistor, method of manufacturing the same, and organic light emitting display device including the same

Patent metadata

Field	Value
Publication number	US-2018190824-A1
Application number	US-201715858679-A
Country	US
Kind code	A1
Filing date	Dec 29, 2017
Priority date	Dec 30, 2016
Publication date	Jul 5, 2018
Grant date	—

Abstract

Disclosed are a thin film transistor, a method of manufacturing the same, and an organic light emitting display device including the same, in which a driving stability of a driving transistor is enhanced even without connecting a source electrode to a bottom gate electrode of the driving transistor. The film transistor includes a N-type semiconductor layer, a P-type semiconductor layer on the N-type semiconductor layer, a first gate electrode on the P-type semiconductor layer, a gate insulation layer between the first gate electrode and the P-type semiconductor layer, a first source electrode connected to a first side of the P-type semiconductor layer, and a first drain electrode connected to a second side of the P-type semiconductor layer.

First claim

What is claimed is:

1 . A thin film transistor comprising:
an N-type semiconductor layer; a P-type semiconductor layer on the N-type semiconductor layer; a first gate electrode over the P-type semiconductor layer; a gate insulation layer between the first gate electrode and the P-type semiconductor layer; a first source electrode connected to a first side of the P-type semiconductor layer; and a first drain electrode connected to a second side of the P-type semiconductor layer.

2 . The thin film transistor of claim 1 , wherein when, a threshold voltage of the N-type semiconductor layer satisfies

Vth

N



1

>

DV
2

,

where Vth N1 is the threshold voltage of the N-type semiconductor layer is and DV is a drain voltage applied to the first drain electrode.

3 . The thin film transistor of claim 1 , wherein
the first source electrode includes a first source electrode layer contacting the P-type semiconductor layer and having a P-type semiconductor characteristic, and a second source electrode layer disposed on the first source electrode layer, and the first drain electrode includes a first drain electrode layer contacting the P-type semiconductor layer and having the P-type semiconductor characteristic, and a second drain electrode layer disposed on the first drain electrode layer.

4 . The thin film transistor of claim 3 , wherein the P-type semiconductor layer, the first source electrode layer, and the first drain electrode layer are formed of the same material.

5 . The thin film transistor of claim 1 , wherein the P-type semiconductor layer has a thickness thinner than a thickness of the N-type semiconductor layer.

6 . The thin film transistor of claim 1 , wherein the N-type semiconductor layer is an N-type oxide semiconductor layer, and the P-type semiconductor layer is a P-type oxide semiconductor layer.

7 . The thin film transistor of claim 6 , wherein the P-type semiconductor layer includes Cu 2 O.

8 . A method of manufacturing a thin film transistor, the method comprising:
forming a first N-type semiconductor layer and a P-type semiconductor layer of a first thin film transistor and a second N-type semiconductor layer of a second thin film transistor, on a first gate insulation layer; forming a second gate insulation layer on the P-type semiconductor layer and forming the second gate insulation on the second N-type semiconductor layer; forming a first gate electrode overlapping the P-type semiconductor layer on the second gate insulation layer and a second gate electrode overlapping the second N-type semiconductor layer on the second gate insulation layer; forming an interlayer dielectric on the first gate electrode and the second gate electrode; forming first and second contact holes exposing a portion of the P-type semiconductor layer to pass through the interlayer dielectric, and third and fourth contact holes exposing a portion of the second N-type semiconductor layer; and forming a first source electrode connected to the P-type semiconductor layer through the first contact hole, a first drain electrode connected to the P-type semiconductor layer through the second contact hole, a second source electrode connected to the second N-type semiconductor layer through the third contact hole, and a second drain electrode connected to the second N-type semiconductor layer through the fourth contact hole, on the interlayer dielectric.

9 . The method of claim 8 , wherein a threshold voltage of the first N-type semiconductor layer satisfies

Vth

N



1

>

DV
2

,

where Vth N1 is the threshold voltage of the first N-type semiconductor layer and DV is a drain voltage applied to the first drain electrode.

10 . The method of claim 8 , wherein the P-type semiconductor layer has a thickness thinner than a thickness of the first N-type semiconductor layer.

11 . The method of claim 8 , wherein the first N-type semiconductor layer and the second N-type semiconductor layer are an N-type oxide semiconductor layer, and the P-type semiconductor layer is a P-type oxide semiconductor layer.

12 . The thin film transistor of claim 11 , wherein the P-type semiconductor layer includes Cu 2 O.

13 . An organic light emitting display device comprising:
a pixel including an organic light emitting diode, a first thin film transistor, and a second thin film transistor, and connected to a scan line and a data line, wherein the first thin film transistor has a first N-type semiconductor layer and a P-type semiconductor layer is disposed on the first N-type semiconductor layer, and the second thin film transistor has a second N-type semiconductor layer.

14 . The organic light emitting display device of claim 13 , wherein a threshold voltage of the first N-type semiconductor layer satisfies

Vth

N



1

>

DV
2

,

where Vth N1 is a threshold voltage of the first N-type semiconductor layer and DV is a source voltage.

15 . The organic light emitting display device of claim 13 , wherein the first thin film transistor further comprises:
a first gate electrode on the P-type semiconductor layer; a gate insulation layer between the first gate electrode and the P-type semiconductor layer; a first source electrode connected to a first side of the P-type semiconductor layer; and a first drain electrode connected to a second side of the P-type semiconductor layer.

16 . The organic light emitting display device of claim 15 , wherein
each of the first and second source electrodes comprises a first source electrode layer contacting the P-type semiconductor layer and having a P-type semiconductor characteristic, and a second source electrode layer disposed on the first source electrode layer, and each of the first and second drain electrodes comprises a first drain electrode layer contacting the P-type semiconductor layer and having the P-type semiconductor characteristic, and a second drain electrode layer disposed on the first drain electrode layer.

17 . The organic light emitting display device of claim 16 , wherein the P-type semiconductor layer, the first source electrode layer, and the first drain electrode layer are forme

Assignees

• Lg Display Co Ltd

Inventors

• Bae Jonguk
• Jang Yongho

Classifications

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H01L29/66969

  Electricity · mapped topic

• H01L29/78648

  Electricity · mapped topic