Semiconductor Devices With Gate-Controlled Energy Filtering

Patent metadata

Field	Value
Publication number	US-2018190818-A1
Application number	US-201615393905-A
Country	US
Kind code	A1
Filing date	Dec 29, 2016
Priority date	Dec 29, 2016
Publication date	Jul 5, 2018
Grant date	—

Abstract

The present disclosure relates to semiconductor devices with gate-controlled energy filtering. One example embodiment includes a semiconductor device. The semiconductor device includes a first electrode, a second electrode, and a channel therebetween. The semiconductor device also includes a first interference structure located in the channel. Further, the semiconductor device includes a first gate for controlling a voltage over the first interference structure. The first interference structure is formed to induce a local mini-band structure that can be shifted by the voltage controlled by the first gate, such that the first local mini-band structure is: (1) aligned with a band structure in the semiconductor device to turn the semiconductor device on; and (2) misaligned with the band structure in the semiconductor device to turn the semiconductor device off

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first electrode; a second electrode; a channel in between the first electrode and the second electrode; a first interference structure located in the channel such that, when a current is flowing from the second electrode to the first electrode, the current passes through the first interference structure; and a first gate for controlling a voltage over the first interference structure, wherein the first interference structure is formed to induce a first local mini-band structure that can be shifted by the voltage controlled by the first gate, such that the first local mini-band structure is:
aligned with a band structure in the semiconductor device to turn the semiconductor device on; and
misaligned with the band structure in the semiconductor device to turn the semiconductor device off

2 . The semiconductor device according to claim 1 , further comprising:
at least one further interference structure located in series with the first interference structure, such that, when the current is flowing from the second electrode to the first electrode, the current passes through the at least one further interference structure, wherein the at least one further interference structure is formed to induce a further local mini-band structure, and wherein the first local mini-band structure can be shifted by the voltage controlled by the first gate such that the first local mini-band structure and the further local mini-band structure are:
aligned to turn on the semiconductor device; and
misaligned to turn the semiconductor device off.

3 . The semiconductor device according to claim 2 , further comprising two interference structures.

4 . The semiconductor device according to claim 2 , further comprising at least one further gate for controlling a voltage over at least one of the at least one further interference structures, wherein the at least one further gate is configured to shift the further local mini-band structure.

5 . The semiconductor device according to claim 4 , wherein the first gate and the at least one further gate are used as logical inputs to the semiconductor device.

6 . The semiconductor device according to claim 2 , wherein the at least one further interference structure is doped.

7 . The semiconductor device according to claim 1 , wherein a doping level of the first electrode is selected such that a Fermi-level of the first electrode and the second electrode lies within or just below a lowest mini-band of the first local mini-band structure induced by the first interference structure.

8 . The semiconductor device according to claim 1 ,
wherein the first interference structure is a super-lattice structure comprising stacks of alternating super-lattice planes, wherein the super-lattice planes are oriented such that, when a current is flowing from the first electrode to the second electrode, a direction of the current flowing from the first electrode to the second electrode is substantially orthogonal to the super-lattice planes.

9 . The semiconductor device according to claim 1 , wherein the semiconductor device is an elongated nanostructure.

10 . The semiconductor device according to claim 9 , wherein the first interference structure is fabricated by locally varying a diameter of the elongated nanostructure.

11 . The semiconductor device according to claim 1 , wherein the semiconductor device is a component of a semiconductor circuit.

12 . A transistor comprising a semiconductor device, wherein the semiconductor device comprises:
a first electrode; a second electrode; a channel in between the first electrode and the second electrode; a first interference structure located in the channel such that, when a current is flowing from the second electrode to the first electrode, the current passes through the first interference structure; and a first gate for controlling a voltage over the first interference structure, wherein the first interference structure is formed to induce a first local mini-band structure that can be shifted by the voltage controlled by the first gate, such that the first local mini-band structure is:
aligned with a band structure in the semiconductor device to turn the semiconductor device on; and
misaligned with the band structure in the semiconductor device to turn the semiconductor device off

13 . The transistor according to claim 12 , wherein the semiconductor device further comprises:
at least one further interference structure located in series with the first interference structure, such that, when the current is flowing from the second electrode to the first electrode, the current passes through the at least one further interference structure, wherein the at least one further interference structure is formed to induce a further local mini-band structure, and wherein the first local mini-band structure can be shifted by the voltage controlled by the first gate such that the first local mini-band structure and the further local mini-band structure are:
aligned to turn on the semiconductor device; and
misaligned to turn the semiconductor device off.

14 . The transistor according to claim 13 , wherein the semiconductor device further comprises two interference structures.

15 . The transistor according to claim 13 ,
wherein the semiconductor device further comprises at least one further gate for controlling a voltage over at least one of the at least one further interference structures, and wherein the at least one further gate is configured to shift the further local mini-band structure.

16 . The transistor according to claim 12 ,
wherein the first electrode is a source, and wherein the second electrode is a drain.

17 . The transistor according to claim 12 , wherein the transistor is a component of a semiconductor circuit.

18 . A method for controlling a semiconductor device, comprising:
controlling a voltage of a first gate to shift a first local mini-band structure such that:
the first local mini-band structure is aligned with a band structure in the semiconductor device to switch the semiconductor device on; or
the first local mini-band structure is misaligned with the band structure in the semiconductor device to switch the semiconductor device off,
wherein the semiconductor device comprises:
a first electrode;
a second electrode;
a channel in between the first electrode and the second electrode; and
a first interference structure located in the channel such that, when a current is flowing from the second electrode to the first electrode, the current passes through the first interference structure,
wherein the first gate is for controlling a voltage over the first interference structure, and wherein the first interference structure is formed to induce the first local mini-band structure, which can be shifted by the voltage controlled by the first gate.

19 . The method according to claim 18 , further comprising:
controlling the voltage of the first gate and a voltage of at least one further gate such that: the first local mini-band structure and a further local mini-band structure are aligned for switching on the semiconductor device; or the first local mini-band structure and the further local mini-band structure are misaligned for switching off the semiconductor device, wherein the semiconductor device further comprises:
at least one further interference structure located in series with the first interference structure, such that, when

Assignees

• Imec Vzw
• Univ Antwerpen

Inventors

• Thewissen Maarten
• Magnus Wim
• Soree Bart

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/0676

  Electricity · mapped topic

• H01L29/41758

  Electricity · mapped topic

• H01L29/1037

  Electricity · mapped topic

• H03K17/162

  without feedback from the output circuit to the control circuit · CPC title