Resistive memory device and method of fabricating the same

US2018190352A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2018190352-A1
Application numberUS-201715859165-A
CountryUS
Kind codeA1
Filing dateDec 29, 2017
Priority dateDec 31, 2016
Publication dateJul 5, 2018
Grant date

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

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A resistive memory device and a fabricating method thereof are provided. The resistive memory device includes: a first electrode electrically coupled with a first wire; a second electrode facing the first electrode and electrically coupled with a second wire, the second electrode including an oxygen vacancy reservoir and a contact electrode, and a memory cell including a variable resistive layer and being disposed between the first electrode and the second electrode. The variable resistive layer has a conductive filament, which includes oxygen vacancies and connects the first electrode and the second electrode. The oxygen vacancy reservoir is disposed on the variable resistive layer, and the contact electrode is coupled to the oxygen vacancy reservoir and the second wire. The oxygen vacancy reservoir has a volume or oxidizing power to exchange a limited amount of oxygen ions and oxygen vacancies required for switching the conductive filament with the variable resistive layer.

First claim

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What is claimed is: 1 . A resistive memory device comprising: a first electrode electrically coupled with a first wire; a second electrode facing the first electrode and electrically coupled with a second wire, the second electrode including a finite oxygen vacancy reservoir and a contact electrode; and a memory cell including a variable resistive layer and being disposed between the first electrode and the second electrode, the variable resistive layer having a conductive filament that includes one or more oxygen vacancies and that connects the first electrode and the second electrode, wherein the finite oxygen vacancy reservoir is disposed on the variable resistive layer, and the contact electrode is coupled to the finite oxygen vacancy reservoir and the second wire, and wherein the finite oxygen vacancy reservoir has a volume or oxidizing power to exchange a limited amount of oxygen ions and oxygen vacancies required for switching the conductive filament with the variable resistive layer. 2 . The resistive memory device according to claim 1 , wherein the variable resistive layer comprises a metal oxide having a stoichiometric composition or an oxygen-deficient composition. 3 . The resistive memory device according to claim 1 , wherein the metal oxide includes at least one selected from the group consisting of tantalum (Ta), scandium (Sc), yttrium (Y), titanium (Ti), zirconium (Zr), vanadium (V), chromium (Cr), niobium (Nb), osmium (Os), manganese (Mn), iron (Fe), nickel (Ni), copper (Cu), silver (Ag), zinc (Zn), hafnium (Hf), and tungsten (W). 4 . The resistive memory device according to claim 1 , wherein the variable resistive layer comprises a metal oxide, and the finite oxygen vacancy reservoir has a lower oxidation potential energy than the metal oxide of the variable resistive layer. 5 . The resistive memory device according to claim 1 , wherein the first electrode comprises a non-reactive metal having a lower oxidizing power than a material in the finite oxygen vacancy reservoir. 6 . The resistive memory device according to claim 1 , wherein the finite oxygen vacancy reservoir includes a metal or an oxide of the metal, the metal including one or more of tantalum (Ta), titanium (Ti), zirconium (Zr), vanadium (V), tungsten (W), and ruthenium (Ru). 7 . The resistive memory device according to claim 1 , wherein the volume of the finite oxygen vacancy reservoir is based on at least one of the number of the one or more oxygen vacancies in the conductive filament, a diameter of the conductive filament, and an oxygen solubility of the finite oxygen vacancy reservoir. 8 . The resistive memory device according to claim 1 , wherein the finite oxygen vacancy reservoir is locally disposed on a partial region of the variable resistive. 9 . The resistive memory device according to claim 1 , wherein a thickness of the finite oxygen vacancy reservoir is within a range of 3 to 20 times of a thickness of the variable resistive layer. 10 . A resistive memory device comprising: a first electrode electrically coupled with a first wire; a second electrode facing the first electrode and being electrically coupled with a second wire; and a memory cell including a variable resistive layer and being disposed between the first electrode and the second electrode, the variable resistive layer having a conductive bridge that includes metal ions and that connects the first electrode and the second electrode, wherein the first electrode includes a contact electrode electrically coupled with the first wire and an ion storage source disposed on the contact electrode, and the ion storage source has a volume or ionization degree to exchange a limited amount of metal ions required for switching the conductive bridge with the variable resistive layer. 11 . The resistive memory device according to claim 10 , wherein the variable resistive layer includes a solid electrolyte comprising at least one of a chalcogenide and a metal oxide. 12 . The resistive memory device according to claim 10 , wherein the volume of the ion storage source is based on at least one of the number of the metal ions in the conductive bridge, a volume of the conductive bridge, and an ionization degree of the conductive bridge. 13 . The resistive memory device according to claim 10 , wherein the ion storage source includes at least any one of silver (Ag), tellurium (Te), copper (Cu), nickel (Ni), and zinc (Zn). 14 . The resistive memory device according to claim 10 , wherein the ion storage source is locally disposed on a portion of the contact electrode. 15 . The resistive memory device according to claim 14 , wherein the ion storage source has a tip portion. 16 . The resistive memory device according to claim 10 , wherein a thickness of the ion storage source is within a range of 3 to 20 times of a thickness of the variable resistive layer. 17 . A method of fabricating a resistive memory device, comprising: providing a conductive layer, the conductive layer being an electrode; forming a screen mask on the conductive layer, the screen mask having openings that expose portions of a surface of the conductive layer; forming, using a physical vapor deposition, an oxygen vacancy reservoir or an ion storage source on the exposed portions of the conductive layer, the oxygen vacancy reservoir or the ion storage source having a tip portion; removing the screen mask; and forming a variable resistive layer on the oxygen vacancy reservoir or the ion storage source. 18 . A method of fabricating a resistive memory device, comprising: providing a variable resistive layer; forming a screen mask on the variable resistive layer, the screen mask having openings that expose portions of a surface of the variable resistive layer; forming, using a physical vapor deposition, an oxygen vacancy reservoir or an ion storage source having a tip portion on the exposed portions of the variable resistive layer; and removing the screen mask.

Assignees

Inventors

Classifications

  • composed of a combination of metals and oxides · CPC title

  • comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] · CPC title

  • by vapour deposition · CPC title

  • Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way · CPC title

  • Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

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What does patent US2018190352A1 cover?
A resistive memory device and a fabricating method thereof are provided. The resistive memory device includes: a first electrode electrically coupled with a first wire; a second electrode facing the first electrode and electrically coupled with a second wire, the second electrode including an oxygen vacancy reservoir and a contact electrode, and a memory cell including a variable resistive laye…
Who is the assignee on this patent?
Sk Hynix Inc, Seoul Nat Univ R&Db Foundation
What technology area does this patent fall under?
Primary CPC classification G11C13/0011. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jul 05 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).