N-way monitor

Patent metadata

Field	Value
Publication number	US-2018189162-A1
Application number	US-201615394271-A
Country	US
Kind code	A1
Filing date	Dec 29, 2016
Priority date	Dec 29, 2016
Publication date	Jul 5, 2018
Grant date	—

Abstract

A processor core includes a decode circuit to decode an instruction, where the instruction specifies an address to be monitored. The processor core further includes a monitor circuit, where the monitor circuit includes a data structure to store a plurality of entries for addresses that are being monitored by the monitor circuit and a triggered queue, where the monitor circuit is to enqueue an address being monitored by the monitor circuit into the triggered queue in response to a determination that a triggering event for the address being monitored by the monitor circuit occurred. The processor core further includes an execution circuit to execute the decoded instruction to add an entry for the specified address to be monitored into the data structure and ensure, using a cache coherence protocol, that a coherency status of a cache line corresponding to the specified address to be monitored is in a shared state.

First claim

What is claimed is:

1 . A processor core comprising:
a decode circuit to decode an instruction, wherein the instruction specifies an address to be monitored; a monitor circuit, wherein the monitor circuit includes a data structure to store a plurality of entries for addresses that are being monitored by the monitor circuit and a triggered queue, wherein the monitor circuit to enqueue an address being monitored by the monitor circuit into the triggered queue in response to a determination that a triggering event for the address being monitored by the monitor circuit occurred; and an execution circuit to execute the decoded instruction to:
add an entry for the specified address to be monitored into the data structure and
ensure, using a cache coherence protocol, that a coherency status of a cache line corresponding to the specified address to be monitored is in a shared state.

2 . The processor core of claim 1 , wherein the execution circuit to return an indication that the specified address to be monitored is already being monitored by the monitor circuit in response to a determination that the entry for the specified address to be monitored exists in the data structure.

3 . The processor core of claim 1 , wherein the execution circuit to return an indication that the data structure is full in response to a determination that there is no free entry available in the data structure.

4 . The processor core of claim 1 , wherein the monitor circuit to free the entry for the specified address to be monitored in response to the determination that the triggering event for the specified address to be monitored occurred.

5 . The processor core of claim 1 , wherein the monitor circuit includes an overflow indicator, and wherein the monitor circuit to set the overflow indicator in response to a determination that the triggered queue has overflowed.

6 . The processor core of claim 1 , wherein the monitor circuit to determine that a triggering event for the specified address being monitored occurred based on a determination that that the coherency status of the cache line corresponding to the specified address to be monitored has changed.

7 . The processor core of claim 1 , wherein the entry for the specified address to be monitored includes an indication of a logical address corresponding to the specified address to be monitored and an indication of a physical address corresponding to the specified address to be monitored.

8 . A method performed by a processor core, comprising:
decoding an instruction, wherein the instruction specifies an address to be monitored; and executing the decoded instruction to add an entry for the specified address to be monitored into a data structure of a monitor circuit and ensure, using a cache coherence protocol, that a coherency status of a cache line corresponding to the specified address to be monitored is in a shared state, wherein the monitor circuit to enqueue the specified address to be monitored into a triggered queue of the monitor circuit in response to a determination that a triggering event for the specified address to be monitored occurred.

9 . The method of claim 8 , wherein the execution to return an indication that the specified address to be monitored is already being monitored by the monitor circuit in response to a determination that the entry for the specified address to be monitored exists in the data structure.

10 . The method of claim 8 , wherein the execution to return an indication that the data structure is full in response to a determination that there is no free entry available in the data structure.

11 . The method of claim 8 , wherein the monitor circuit to free the entry for the specified address to be monitored in response to the determination that the triggering event for the specified address to be monitored occurred.

12 . The method of claim 8 , wherein the monitor circuit includes an overflow indicator, and wherein the monitor circuit to set the overflow indicator in response to a determination that the triggered queue has overflowed.

13 . The method of claim 8 , wherein the monitor circuit to determine that a triggering event for the specified address being monitored occurred based on a determination that that the coherency status of the cache line corresponding to the specified address to be monitored has changed.

14 . The method of claim 8 , wherein the entry for the specified address to be monitored includes an indication of a logical address corresponding to the specified address to be monitored and an indication of a physical address corresponding to the specified address to be monitored.

15 . A non-transitory computer-readable storage medium having stored therein instructions, which when executed by a processor core, causes the processor core to:
decode the instruction, wherein the instruction specifies an address to be monitored; and execute the decoded instruction to add an entry for the specified address to be monitored into a data structure of a monitor circuit and ensure, using a cache coherence protocol, that a coherency status of a cache line corresponding to the specified address to be monitored is in a shared state, wherein the monitor circuit to enqueue the specified address to be monitored into a triggered queue of the monitor circuit in response to a determination that a triggering event for the specified address to be monitored occurred.

16 . The non-transitory computer-readable storage medium of claim 15 , wherein the execution to return an indication that the specified address to be monitored is already being monitored by the monitor circuit in response to a determination that the entry for the specified address to be monitored exists in the data structure.

17 . The non-transitory computer-readable storage medium of claim 15 , wherein the execution to return an indication that the data structure is full in response to a determination that there is no free entry available in the data structure.

18 . The non-transitory computer-readable storage medium of claim 15 , wherein the monitor circuit to free the entry for the specified address to be monitored in response to the determination that the triggering event for the specified address to be monitored occurred.

19 . The non-transitory computer-readable storage medium of claim 15 , wherein the monitor circuit includes an overflow indicator, and wherein the monitor circuit to set the overflow indicator in response to a determination that the triggered queue has overflowed.

20 . The non-transitory computer-readable storage medium of claim 15 , wherein the monitor circuit to determine that a triggering event for the specified address being monitored occurred based on a determination that that the coherency status of the cache line corresponding to the specified address to be monitored has changed.

21 . The non-transitory computer-readable storage medium of claim 15 , wherein the entry for the specified address to be monitored includes an indication of a logical address corresponding to the specified address to be monitored and an indication of a physical address corresponding to the specified address to be monitored.

Assignees

• Intel Corp

Inventors

• Heirman Wim
• Vandriessche Yves

Classifications

• G06F2201/885

  Monitoring specific for caches · CPC title

• G06F11/3055

  Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16) · CPC title

• G06F11/3037 Primary

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F9/3818

  Decoding for concurrent execution · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title