Solar cells having differentiated p-type and n-type architectures

Patent metadata

Field	Value
Publication number	US-2018175221-A1
Application number	US-201615384061-A
Country	US
Kind code	A1
Filing date	Dec 19, 2016
Priority date	Dec 19, 2016
Publication date	Jun 21, 2018
Grant date	—

Abstract

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an N-type semiconductor substrate having a light-receiving surface and a back surface. A plurality of N-type polycrystalline silicon regions is disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate. A plurality of P-type polycrystalline silicon regions is disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate.

First claim

What is claimed is:

1 . A solar cell, comprising:
an N-type semiconductor substrate having a light-receiving surface and a back surface; a plurality of N-type polycrystalline silicon regions disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate; and a plurality of P-type polycrystalline silicon regions disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate, wherein a total area of the plurality of N-type polycrystalline silicon regions is greater than a total area of the plurality of P-type polycrystalline silicon regions in the plurality of corresponding trenches.

2 . The solar cell of claim 1 , wherein the total area of the plurality of N-type polycrystalline silicon regions is greater than the total area of the plurality of P-type polycrystalline silicon regions in the plurality of corresponding trenches by a ratio of 15:1 or more.

3 . The solar cell of claim 1 , wherein the plurality of P-type polycrystalline silicon regions overlap a portion of the plurality of N-type polycrystalline silicon regions.

4 . The solar cell of claim 1 , wherein each of the plurality of N-type polycrystalline silicon regions has a width greater than a width of each of the plurality of P-type polycrystalline silicon regions by a ratio of 5:1 or more.

5 . The solar cell of claim 1 , wherein each of the plurality of N-type polycrystalline silicon regions has a thickness relative to a thickness of each of the plurality of P-type polycrystalline silicon regions by a ratio of 3:1 or less.

6 . The solar cell of claim 1 , wherein each of the plurality of trenches has a depth approximately in the range of 0.1-3 microns from the back surface and into the N-type semiconductor substrate.

7 . The solar cell of claim 1 , wherein each of the plurality of trenches has a texturized surface.

8 . The solar cell of claim 1 , further comprising:
a third thin dielectric layer disposed laterally directly between adjacent ones of the N-type polycrystalline silicon regions and the P-type polycrystalline silicon regions.

9 . The solar cell of claim 1 , further comprising:
a plurality of conductive contact structures electrically connected to the N-type polycrystalline silicon regions and the P-type polycrystalline silicon regions.

10 . A solar cell, comprising:
an N-type semiconductor substrate having a light-receiving surface and a back surface; a plurality of N-type polycrystalline silicon regions disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate; and a plurality of P-type polycrystalline silicon regions disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate, wherein each of the plurality of N-type polycrystalline silicon regions has a thickness relative to a thickness of each of the plurality of P-type polycrystalline silicon regions by a ratio of 3:1 or less.

11 . The solar cell of claim 10 , wherein the thickness of each of the plurality of N-type polycrystalline silicon regions is 1000 Angstroms or less, and the thickness of each of the plurality of P-type polycrystalline silicon regions is approximately 300 Angstroms.

12 . The solar cell of claim 10 , wherein the plurality of P-type polycrystalline silicon regions overlap a portion of the plurality of N-type polycrystalline silicon regions.

13 . The solar cell of claim 10 , wherein each of the plurality of trenches has a depth approximately in the range of 0.1-3 microns from the back surface and into the N-type semiconductor substrate.

14 . The solar cell of claim 10 , wherein each of the plurality of trenches has a texturized surface.

15 . The solar cell of claim 10 , further comprising:
a third thin dielectric layer disposed laterally directly between adjacent ones of the N-type polycrystalline silicon regions and the P-type polycrystalline silicon regions.

16 . The solar cell of claim 10 , further comprising:
a plurality of conductive contact structures electrically connected to the N-type polycrystalline silicon regions and the P-type polycrystalline silicon regions.

17 . A method of fabricating a solar cell, the method comprising:
forming an N-type silicon layer on a first thin dielectric layer formed on a back surface of a substrate, the substrate having a light-receiving surface and the back surface, wherein the N-type silicon layer is formed using an in situ doping chemical vapor deposition (CVD) process; forming an insulator layer on the N-type silicon layer; forming a plurality of openings in the insulator layer and the N-type silicon layer and a corresponding plurality of trenches in the back surface of the substrate; and forming a P-type silicon layer on a second thin dielectric layer formed in the plurality of trenches using a solid-state doping process.

18 . The method of claim 17 , wherein forming the plurality of openings and the corresponding plurality of trenches comprises applying a laser ablation process.

19 . The method of claim 17 , further comprising:
prior to forming the P-type silicon layer and the second thin dielectric layer in the plurality of trenches, texturizing a bottom surface of each of the plurality of trenches.

20 . A solar cell fabricated according to the method of claim 17 .

Assignees

• Sunpower Corp

Inventors

• Smith David D
• Waldhauer Ann
• Balu Venkatasubramani
• Tracy Kieran Mark

Classifications

• H01L31/1804

  Electricity · mapped topic

• H01L31/03682

  Electricity · mapped topic

• H01L31/068

  Electricity · mapped topic

• H01L31/02363 Primary

  Electricity · mapped topic

• H10F77/1642

  including only Group IV materials · CPC title