Charge pump circuit

Patent metadata

Field	Value
Publication number	US-2018166986-A1
Application number	US-201715838181-A
Country	US
Kind code	A1
Filing date	Dec 11, 2017
Priority date	Dec 14, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

A charge pump circuit includes N boosting circuits, (N-2) switching circuits and a control circuit. A k th boosting circuit includes a unidirectional component and a capacitor. A positive terminal of the unidirectional component of the k th boosting circuit is electrically connected to a negative terminal of a unidirectional component of a (k-1) th boosting circuit. A first terminal of the capacitor of the k th boosting circuit is electrically connected to a negative terminal of the unidirectional component of the k th boosting circuit. A (2i-1) th switching circuit selectively conducts a current path from a (2i-1) th boosting circuit to a first clock terminal or to a ground terminal according to a control signal of the control circuit. A (2i) th switching circuit selectively conducts a current path from a (2i) th boosting circuit to a second clock terminal or to the ground terminal according to the control signal of the control circuit.

First claim

What is claimed is:

1 . A charge pump circuit, comprising:
N boost circuits, with N being a positive integer greater than 2, and a k th boost circuit of the N boost circuits, with k being a positive integer not greater than N, wherein the k th boost circuit comprises:
an unidirectional component having a positive terminal and a negative terminal, with the positive terminal of the unidirectional component of the k th boost circuit electrically connected to the negative terminal of the unidirectional component of a (k-1) th boost circuit; and
a capacitor having a first terminal and a second terminal, with the first terminal electrically connected to the negative terminal of the unidirectional component of the k th boost circuit;
a control circuit configured to provide at least one set of control signals; and (N-2) switch circuits, with a (2i-1) th switch circuit of the (N-2) switch circuits electrically connected to a (2i-1) th boost circuit of the N boost circuits, the (2i-1) th switch circuit selectively forming a current path from the (2i-1) th boost circuit to a first clock terminal or another current path from the (2i-1) th boost circuit to a ground terminal according to the set of control signals, a 2i th switch circuit of the (N-2) switch circuits electrically connected to a 2i th boost circuit of the N boost circuits, the 2i th switch circuit selectively forming a current path from the 2i th boost circuit to a second clock terminal or another current path from the 2i th boost circuit to a ground terminal according to the set of control signals, and i being a positive integer less than N/2; wherein the second terminal of the capacitor of a (N-1) th boost circuit of the N boost circuits is electrically connected to the second clock terminal, and the second terminal of the capacitor of a N th boost circuit of the N boost circuits is electrically connected to the ground terminal.

2 . The charge pump circuit according to claim 1 , wherein the first clock terminal provides a first clock signal, the second clock terminal provides a second clock signal, and the second clock signal and the first clock signal are inverted relative to each other.

3 . The charge pump circuit according to claim 1 , wherein the first clock terminal provides a first clock signal, the second clock terminal provides a second clock signal, and the second clock signal and the first clock signal are separated from each other.

4 . The charge pump circuit according to claim 1 , wherein each switch circuit comprises a multiplexer having a first input terminal, a second input terminal, an output terminal and a receiving terminal, the receiving terminal of the multiplexer of each switch circuit is electrically connected to the control circuit, the second input terminal of the multiplexer of each switch circuit is electrically connected to the ground terminal, the first input terminal of the multiplexer of the (2i-1) th switch circuit is electrically connected to the first clock terminal, the output terminal of the multiplexer of the (2i-1) th switch circuit is electrically connected to the (2i-1) th boost circuit, the first input terminal of the multiplexer of the (2i) th switch circuit is electrically connected to the second clock terminal, and the output terminal of the multiplexer of the (2i) th switch circuit is electrically connected to the (2i) th boost circuit.

5 . The charge pump circuit according to claim 1 , wherein the unidirectional component is a diode.

6 . The charge pump circuit according to claim 1 , wherein the unidirectional component is a diode-connected transistor.

7 . The charge pump circuit according to claim 1 , wherein a capacitance of the N th boost circuit is greater than a capacitance of the (N-1) th boost circuit.

8 . The charge pump circuit according to claim 1 , wherein capacitances of the first boost circuit to the (N-1) t boost circuit are substantially the same.

9 . The charge pump circuit according to claim 1 , wherein capacitances of the first boost circuit to the (N-1)th boost circuit are incremental.

Assignees

• Silicon Integrated Systems Corp

Inventors

• Lin Wen-Chi
• Wu Cheng-Ta
• Chen Keng-Nan

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/075

  including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages · CPC title

• H02M3/073

  Charge pumps of the Schenkel-type · CPC title