Thin Film Transistor, Array Substrate, Method for Manufacturing the Same, and Display Device

Patent metadata

Field	Value
Publication number	US-2018166584-A9
Application number	US-201615169021-A
Country	US
Kind code	A9
Filing date	May 31, 2016
Priority date	Jun 15, 2015
Publication date	Jun 14, 2018
Grant date	—

Abstract

Disclosed is a thin film transistor, an array substrate, a method for manufacturing the same, and a display device. The method includes: forming a source and drain on a base substrate and forming a semiconductor layer. Between the step of forming the source and drain and the step of forming the semiconductor layer, the method further includes: forming a diffusion barrier layer. Metal atoms diffused from the source and drain and passing through the diffusion barrier layer react with a part of the semiconductor layer near the source and drain, and a metal transition layer containing metal silicide is formed.

First claim

1 . A method for manufacturing a thin film transistor, comprising:
forming a source and drain on a base substrate; forming a semiconductor layer; and between forming the source and drain and forming the semiconductor layer, the method further comprises:
forming a diffusion barrier layer, wherein metal atoms diffused from the source and drain and passing through the diffusion barrier layer react with a part of the semiconductor layer near the source and drain, and a metal transition layer containing metal silicide is formed, wherein the metal silicide comprises the metal atoms diffused from the source and drain.

2 . The method for manufacturing the thin film transistor according to claim 1 , wherein a material of the semiconductor layer is amorphous silicon.

3 . The method for manufacturing the thin film transistor according to claim 2 , wherein the diffusion barrier layer is formed between the source and drain and the semiconductor layer, and the diffusion barrier layer is configured to block a part of the metal atoms diffused from the source and drain to the semiconductor layer.

4 . The method for manufacturing the thin film transistor according to claim 1 , wherein the metal transition layer is formed in a part of the semiconductor layer near the diffusion barrier layer.

5 . The method for manufacturing the thin film transistor according to claim 1 , wherein the metal atom is copper atom.

6 . The method for manufacturing the thin film transistor according to claim 2 , wherein a material of the diffusion barrier layer comprises at least one of tantalum nitride, titanium nitride, molybdenum nitride, silicon oxynitride, or silicon oxide.

7 . The method for manufacturing the thin film transistor according to claim 2 , wherein after forming the diffusion barrier layer, the method further comprises:
annealing the base substrate on which the source and drain, the diffusion barrier layer and the semiconductor layer are formed, such that the reaction between the metal atoms passing through the diffusion barrier layer and the amorphous silicon in the semiconductor layer is accelerated, and the metal transition layer containing metal silicide is formed.

8 . The method for manufacturing the thin film transistor according to claim 7 , wherein the base substrate is annealed at a temperature from 200° C. to 450° C.

9 . The method for manufacturing the thin film transistor according to claim 1 , wherein the source and drain, the semiconductor layer, and the diffusion barrier layer is formed in this order:
forming the source and drain on the substrate; forming the diffusion barrier layer overlaying the source and drain; and forming the semiconductor layer on the diffusion barrier layer.

10 . A method for manufacturing an array substrate, comprising the method for manufacturing the thin film transistor according to claim 1 .

11 . A thin film transistor, comprising:
a base substrate; a source and drain disposed on the base substrate; a diffusion barrier layer disposed on the source and drain; and a semiconductor layer disposed on the diffusion barrier layer, wherein metal atoms diffused from the source and drain and passing through the diffusion barrier layer react with a part of the semiconductor layer near the source and drain, and a metal transition layer containing metal silicide is formed, wherein the metal silicide comprises the metal atoms diffused from the source and drain.

12 . The thin film transistor according to claim 11 , wherein a material of the semiconductor layer is amorphous silicon.

13 . The thin film transistor according to claim 12 , wherein the diffusion barrier layer is configured to block a part of the metal atoms diffused from the source and drain to the semiconductor layer.

14 . The thin film transistor according to claim 11 , wherein the metal transition layer is formed in a part of the semiconductor layer near the diffusion barrier layer.

15 . An array substrate, comprising the thin film transistor according to claim 11 .

16 . A display device, comprising the array substrate according to claim 15 .

17 . The method for manufacturing the thin film transistor according to claim 1 , wherein the part of the semiconductor layer near the source and drain is a part of the semiconductor layer nearer to the source and drain than to a gap between the source and drain.

18 . The thin film transistor according to claim 11 , wherein the part of the semiconductor layer near the source and drain is a part of the semiconductor layer nearer to the source and drain than to a gap between the source and drain

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Han Junhao
• Yin Bingkun
• Ma Jun
• Zhang Min

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D30/0321 Primary

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H01L29/7845

  Electricity · mapped topic

• H01L29/66765

  Electricity · mapped topic

• H01L21/28518

  Electricity · mapped topic