Semiconductor devices including exposed opposing die pads

Patent metadata

Field	Value
Publication number	US-2018166366-A1
Application number	US-201615375812-A
Country	US
Kind code	A1
Filing date	Dec 12, 2016
Priority date	Dec 12, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

A semiconductor device includes a first lead frame, a second lead frame, a first semiconductor chip, and an encapsulation material. The first lead frame includes a first die pad having a first surface and a second surface opposite to the first surface. The second lead frame includes a second die pad having a first surface and a second surface opposite to the first surface. The first surface of the second die pad faces the first surface of the first die pad. The first semiconductor chip is attached to the first surface of the first die pad. The encapsulation material encapsulates the first semiconductor chip and portions of the first lead frame and the second lead frame. The encapsulation material has a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.

First claim

1 . A semiconductor device comprising:
a first lead frame comprising a first die pad having a first surface and a second surface opposite to the first surface of the first die pad; a second lead frame comprising a second die pad having a first surface and a second surface opposite to the first surface of the second die pad, the first surface of the second die pad facing the first surface of the first die pad; a first semiconductor chip attached to the first surface of the first die pad; and an encapsulation material encapsulating the first semiconductor chip and portions of the first lead frame and the second lead frame, the encapsulation material having a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.

2 . The semiconductor device of claim 1 , further comprising:
a second semiconductor chip attached to the first surface of the second die pad.

3 . The semiconductor device of claim 2 , wherein the first semiconductor chip is electrically coupled to the second semiconductor chip.

4 . The semiconductor device of claim 1 , wherein the first lead frame is electrically coupled to the second lead frame.

5 . The semiconductor device of claim 1 , further comprising:
bond wires electrically coupling the first semiconductor chip to leads of the first lead frame.

6 . The semiconductor device of claim 1 , further comprising:
a hole through the encapsulation material extending from the first surface of the encapsulation material to the second surface of the encapsulation material.

7 . The semiconductor device of claim 1 , wherein the semiconductor device is a through-hole device.

8 . The semiconductor device of claim 1 , wherein the semiconductor device is a surface mount device.

9 . A semiconductor device comprising:
a first lead frame comprising a first die pad having a first surface and a second surface opposite to the first surface of the first die pad; a second lead frame comprising a second die pad having a first surface and a second surface opposite to the first surface of the second die pad, the first surface of the second die pad facing the first surface of the first die pad; a first semiconductor chip attached to the first surface of the first die pad; a second semiconductor chip attached to the first surface of the second die pad; and an encapsulation material encapsulating the first semiconductor chip and the second semiconductor chip and portions of the first lead frame and the second lead frame, the encapsulation material having a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.

10 . The semiconductor device of claim 9 , further comprising:
a third semiconductor chip; and a fourth semiconductor chip; wherein the first lead frame comprises a third die pad having a first surface and a second surface opposite to the first surface of the third die pad; wherein the second lead frame comprises a fourth die pad having a first surface and a second surface opposite to the first surface of the fourth die pad; wherein the third semiconductor chip is attached to the first surface of the third die pad; wherein the fourth semiconductor chip is attached to the first surface of the fourth die pad; and wherein the encapsulation material encapsulates the third semiconductor chip and the fourth semiconductor chip and wherein the first surface of the encapsulation material is aligned with the second surface of the third die pad and the second surface of the encapsulation material is aligned with the second surface of the fourth die pad.

11 . The semiconductor device of claim 9 , wherein the first semiconductor chip comprises a power semiconductor chip; and
wherein the second semiconductor chip comprises a logic chip.

12 . The semiconductor device of claim 9 , wherein the first semiconductor chip comprises a power transistor chip; and
wherein the second semiconductor chip comprises a diode chip.

13 . The semiconductor device of claim 9 , wherein the first semiconductor chip comprises a first power transistor chip; and
wherein the second semiconductor chip comprises a second power transistor chip.

14 . The semiconductor device of claim 9 , further comprising:
an interconnect board between the first semiconductor chip and the second semiconductor chip electrically coupling the first semiconductor chip to the second semiconductor chip.

15 . A method to fabricate a semiconductor device, the method comprising:
attaching a first semiconductor chip to a first surface of a first die pad of a first lead frame, the first die pad having a second surface opposite to the first surface of the first die pad; attaching a second semiconductor chip to a first surface of a second die pad of a second lead frame, the second die pad having a second surface opposite to the first surface of the second die pad; stacking the second lead frame on the first lead frame such that the first surface of the first die pad faces the first surface of the second die pad; and encapsulating the first semiconductor chip and the second semiconductor chip and portions of the first lead frame and the second lead frame with an encapsulation material such that the second surface of the first die pad is aligned with a first surface of the encapsulation material and the second surface of the second die pad is aligned with a second surface of the encapsulation material.

16 . The method of claim 15 , further comprising:
electrically coupling the second lead frame to the first lead frame.

17 . The method of claim 15 , further comprising:
cutting leads of the second lead frame after stacking the second lead frame on the first lead frame.

18 . The method of claim 15 , further comprising:
wire bonding the first semiconductor chip to leads of the first lead frame; and wire bonding the second semiconductor chip to leads of the second lead frame.

19 . The method of claim 15 , further comprising:
electrically coupling the first semiconductor chip to the second semiconductor chip.

20 . The method of claim 15 , further comprising:
attaching a first heat sink to the second surface of the first die pad and the first surface of the encapsulation material; and attaching a second heat sink to the second surface of the second die pad and the second surface of the encapsulation material.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Fuergut Edward
• Gruber Martin
• Scholz Wolfgang
• Otremba Ralf

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title