Innovative approach to minimize plasma doping induced fin height loss

Patent metadata

Field	Value
Publication number	US-2018166341-A1
Application number	US-201615376719-A
Country	US
Kind code	A1
Filing date	Dec 13, 2016
Priority date	Dec 13, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

A plasma doping process provides conformal doping profiles for lightly doped source/drain regions in fins, and reduces the plasma doping induced fin height loss. The plasma doping process overcomes the limitations caused by traditional plasma doping processes in fin structures that feature aggressive aspect ratios and tights pitches. Semiconductor devices with conformal lightly doped S/D regions and reduced fin height loss demonstrate reduced parallel resistance (Rp) and improved transistor performance.

First claim

1 . A method, comprising:
forming a plurality of fins over a substrate, each fin of the plurality of fins having a. top surface and a pair of opposing side surfaces; forming a gate structure on a fin of the plurality of fins, the gate structure having a first sidewall and a second sidewall; forming a first offset spacer on the first sidewall and a second offset spacer on the second sidewall; forming a first doped source/drain (S/D) region adjacent to the first sidewall and a second doped S/D region adjacent to the second sidewall by doping the top and side surfaces of each fin with a multiple-cycle plasma doping process comprising one or more radio frequency (RF) plasma power pulses; and applying a DC bias voltage to the substrate for a predetermined number of the one or more RF plasma power pulses, wherein the DC bias voltage is ramped at a nominally constant rate.

2 . (canceled)

3 . The method of claim 1 , wherein forming the gate structure comprises forming a gate dielectric on the fin and forming a gate electrode over the gate dielectric.

4 . The method of claim 1 , wherein forming the first offset spacer and the second offset spacer comprises depositing an offset spacer material on the first sidewall and the second sidewall.

5 . The method of claim 1 , further comprising performing a spike anneal at a temperature between 900° C. and 1200° C.

6 . The method of claim 1 , wherein forming the first and the second doped S/D regions comprises introducing at least one dopant species into the fin.

7 . (canceled)

8 . The method of claim 1 , wherein the DC bias voltage is ramped from −0.5 kV to −1.5 kV.

9 . The method of claim 1 , wherein each of the one or more RF plasma power pulses has a duration between 1 μs and 200 μs.

10 . A method comprising:
receiving a substrate with fins thereon, each fin having a top surface, a pair of opposing side surfaces, and a gate structure disposed thereon; exposing the substrate to a multiple-cycle plasma doping process that comprises one or more RF plasma power pulses; and applying a DC bias voltage to the substrate, wherein the applying the DC bias voltage comprises:
maintaining the DC bias voltage at a first nominally constant voltage for a first number of the one or more RF plasma power cycles;
ramping the DC bias voltage at a nominally constant ramping rate for a second number of the one or more RF plasma power cycles; and
maintaining the DC bias voltage at a second nominally constant voltage for a third number of the one or more RF plasma power cycles.

11 . The method of claim 10 , wherein each of the one or more RF plasma power pulses has a magnitude between 200 to 1000 Watts.

12 . The method of claim 10 , wherein each of the one or more RF plasma power pulses varies between a first value and a second value at a frequency of 5 kHz.

13 . The method of claim 10 , wherein the first nominally constant voltage at −0.5 kV.

14 . The method of claim 10 , wherein the second nominally constant voltage value is at −1.5 kV.

15 . The method of claim 10 , wherein the exposing the substrate to the multiple-cycle plasma doping process comprises doping the top surface and the pair of opposing side surfaces of each fin with a dopant concentration of each fin of more than 3×10 19 atoms/cm 3 .

16 . The method of claim 10 , wherein the exposing the substrate to the multiple-cycle plasma doping process comprises reducing a silicon loss from the top surface of each fin by less than 2.3 nm.

17 . The method of claim 10 , wherein the first number of the one or more RF plasma power cycles, the second number of the one or more RF plasma power cycles, and the third number of the one or more RF plasma power cycles are different.

18 . (canceled)

19 . A method comprising:
receiving a substrate with a fins thereon, each fin having a top surface, a pair of opposing side surfaces, and a gate structure disposed thereon; exposing the substrate to a multiple-cycle plasma doping process, wherein the multiple-cycle plasma doping process comprises RF plasma power pulses; and applying a DC bias voltage to the substrate, wherein the applying the DC bias voltage comprises: maintaining the DC bias voltage at a nominally constant voltage value for a first number of RF plasma power pulses; and ramping the DC bias voltage at a nominally constant rate for a second number of RF plasma power pulses.

20 . The method of claim 19 , the maintaining the DC bias voltage at the nominally constant voltage value comprises doping, with a first dopant dose, the top and the pair of opposing side surfaces of each fin.

21 . The method of claim 20 , wherein the ramping the DC bias voltage at the nominally constant rate comprises doping, with a second dopant dose, the top and the pair of opposing side surfaces of each fin, wherein the first and the second dopant doses are different.

22 . The method of claim 19 , wherein the nominally constant voltage value is −0.5 KV.

23 . The method of claim 19 , wherein the applying the DC bias voltage further comprises maintaining the DC bias voltage at another nominally constant voltage value for a third number of RF plasma power pulses.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chan Chia-Ling
• Wang Tsan-Chun
• Chen Liang-Yin
• Chang Huicheng

Classifications

• H10P32/1204 Primary

  from a plasma phase · CPC title

• H01L21/823431 Primary

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic

• H01L21/84

  Electricity · mapped topic

• H01L21/2236

  Electricity · mapped topic