BiMOS DEVICE WITH A FULLY SELF-ALIGNED EMITTER-SILICON AND METHOD FOR MANUFACTURING THE SAME

Patent metadata

Field	Value
Publication number	US-2018166338-A1
Application number	US-201715798972-A
Country	US
Kind code	A1
Filing date	Oct 31, 2017
Priority date	Apr 30, 2015
Publication date	Jun 14, 2018
Grant date	—

Abstract

A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.

First claim

1 - 17 . (canceled)

18 . A BiMOS device, comprising:
a substrate of a first conductive type; a MOS device arranged on a surface region of the substrate in a MOS region; a layer stack arranged on the surface region of the substrate and on the MOS device in the MOS region, wherein the layer stack comprises a first isolation layer arranged on the surface region of the substrate and in the MOS region on the MOS device, a contact layer of the first conductive type arranged on the first isolation layer and a second isolation layer arranged on the contact layer, wherein the layer stack comprises in a bipolar region, different from the MOS region, a window formed in the layer stack through the second isolation layer, the contact layer and the first isolation layer up to the surface region of the substrate; and a bipolar junction transistor arranged on the surface region of the substrate in the bipolar region, wherein the bipolar junction transistor comprises a collector layer of a first semi conductive type arranged on the substrate within the window of the layer stack, a base layer of a second semi conductive type arranged on the collector layer within the window of the layer stack, and an emitter layer or an emitter layer stack comprising the emitter layer arranged on the base layer within the window of the layer stack, wherein the emitter layer is of the first semi conductive type; wherein a distance between the surface region of the substrate and an upper surface region of the emitter layer or emitter layer stack of the bipolar junction transistor is smaller than a sum of a distance between the surface region of the substrate and an upper surface region of the contact layer in the bipolar region and a distance between the surface region of the substrate and an upper surface region of the MOS device in the MOS region.

19 . The BiMOS device according to claim 18 , wherein a distance between the surface region of the substrate and an upper surface region of the emitter layer or emitter layer stack of the bipolar junction transistor is smaller than a sum of a distance between the surface region of the substrate and an upper surface region of the first isolation layer in the bipolar region and a distance between the surface region of the substrate and the upper surface region of the MOS device in the MOS region.

20 . The BiMOS device according to claim 18 , wherein a distance between the surface region of the substrate and an upper region of the emitter layer or emitter layer stack of the bipolar junction transistor is smaller than or equal to a distance between the surface region of the substrate and an upper surface region of the MOS device.

21 . The BiMOS device according to claim 18 , wherein a distance between a face of the window facing the MOS device and a face of a gate of the MOS device facing the bipolar junction transistor is equal to or smaller than 3 m

22 . The BiMOS device according to claim 18 , wherein a distance between a face of the window facing the MOS device and a face of a gate of the MOS device facing the bipolar junction transistor is equal to or smaller than 1,5 μm.

23 . The BiMOS device according to claim 18 , wherein a distance between a face of the window facing the MOS device and a face of a gate of the MOS device facing the bipolar junction transistor is equal to or smaller than 1 μm.

24 . The BiMOS device according to claim 18 , wherein a distance between a face of the window facing the MOS device and a face of a gate of the MOS device facing the bipolar junction transistor is equal to or smaller than 500 nm.

25 . The BiMOS device according to claim 18 , wherein a distance between a face of the window facing the MOS device and a face of a gate of the MOS device facing the bipolar junction transistor is equal to or smaller than 200 nm.

Assignees

• Infineon Technologies Ag

Inventors

• Hoffmann Frank
• Manger Dirk
• Pribil Andreas
• Probst Marc
• Tegen Stefan

Classifications

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H01L29/0821

  Electricity · mapped topic

• H01L29/0804

  Electricity · mapped topic

• H01L29/7371

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic