Multi-metal fill with self-align patterning

Patent metadata

Field	Value
Publication number	US-2018166330-A1
Application number	US-201715498259-A
Country	US
Kind code	A1
Filing date	Apr 26, 2017
Priority date	Dec 12, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

First claim

1 . A method comprising:
providing a substrate; forming a dielectric layer over the substrate; forming a first pattern structure and a second pattern structure over the dielectric layer, wherein each of the first and second pattern structures comprises a first spacer, a second spacer, and a center portion between the first and second spacers; forming a first opening in the dielectric layer, wherein the first opening self-aligns to a space between the first and second pattern structures; depositing a first conductive material in the first opening; removing the center portion of the second pattern structure to form a void above the dielectric layer and between the first and second spacers of the second pattern structure; forming a second opening in the dielectric layer, wherein the second opening self-aligns to the void; and depositing a second conductive material in the second opening, wherein the second conductive material is different from the first conductive material.

2 . The method of claim 1 , wherein the substrate comprises:
a contact metal layer for at least one transistor; a first interconnect layer over the contact metal layer, wherein the dielectric layer is over the first interconnect layer.

3 . The method of claim 1 , wherein depositing the first conductive material comprises forming at least one of a via and a line in the first opening.

4 . The method of claim 1 , wherein depositing the second conductive material comprises forming at least one of a via and a line in the second opening.

5 . The method of claim 1 , further comprising:
after depositing the second conductive material in the second opening, removing the first and second pattern structures; and removing a portion of the first conductive material, a portion of the second conductive material, and a portion of the dielectric layer.

6 . The method of claim 1 , wherein the first and second conductive materials comprise copper, cobalt, aluminum, or graphene.

7 . The method of claim 1 , further comprising:
prior to removing the center portion of the second pattern structure, selectively growing a metal oxide layer on the first conductive material to provide an etch stop capping layer on the first conductive material.

8 . A fabrication method comprising:
providing a substrate; forming a dielectric layer over the substrate; forming a first pattern structure and a second pattern structure over the dielectric layer, wherein each of the first and second pattern structures comprises a first spacer, a second spacer, and a center portion between the first and second spacers; forming a photoresist layer over the first and second photoresist structures; forming first openings in the photoresist layer to expose the center portions of the first and second patterned structures, wherein the first openings are larger than the center portions of the first and second patterned structures and overlap with the first and second spacers of the first and second patterned structures; removing the center portions from the first and second pattern structures through the first openings to form second openings smaller than the first openings between the first and second spacers of the first and second pattern structures; etching portions of the dielectric layer under the second openings; and depositing a conductive material to fill the second openings and to form a first interconnect layer; and removing the photoresist layer.

9 . The method of claim 8 , further comprising:
etching a portion of the dielectric layer between the first and second pattern structures to form another opening, wherein the another opening aligns to the first or second spacer of the first pattern structure and to the first or second spacer of the second pattern structure; and depositing another conductive material to fill the another opening and to form a second interconnect layer, wherein the another conductive material is different from the conductive material for the first interconnect layer.

10 . The method of claim 8 , wherein the substrate comprises:
at least one transistor with a contact metal layer; and a third interconnect layer over the contact metal layer, wherein the dielectric layer is over the third interconnect layer.

11 . The method of claim 9 , further comprising:
removing the first and second spacers of the first and second pattern structures; and removing a portion of the first and second interconnect layers, and a portion of the dielectric layer.

12 . The method of claim 8 , wherein the first interconnect layer comprises lines and vias.

13 . The method of claim 9 , wherein the second interconnect layer comprises lines and vias.

14 . The method of claim 9 , wherein the conductive material and the another conductive matedal comprise copper, cobalt, aluminum, or graphene.

15 . The method of claim 7 , wherein the metal oxide layer comprise aluminum-based oxides or cobalt-based oxides.

16 . (canceled) 16 - 20 .

21 . A method comprising:
providing one or more interconnect layers over a substrate and a dielectric layer over the one or more interconnect layers; forming pattern structures, wherein each of the pattern structures comprises a center portion between a first spacer and a second spacer; forming first openings in the dielectric layer, wherein the first openings self-align to a space between the pattern structures; depositing a first conductive material in the first openings; removing the center portion for each of the pattern structures to form voids above the dielectric layer and between the first and the second spacers of each of the pattern structures; forming second openings in the dielectric layer, wherein the second openings self-align to the voids; and depositing a second conductive material different from the first conductive material in the second openings.

22 . The method of claim 21 , wherein depositing the first conductive material comprises forming vias and lines in the first openings.

23 . The method of claim 21 , wherein depositing the second conductive material comprises forming vias and lines in the second openings.

24 . The method of claim 21 , wherein the first and second conductive materials comprise copper, cobalt, aluminum, or graphene.

25 . The method of claim 21 , further comprising:
prior to removing the center portion of each of the pattern structures, selectively growing a metal oxide layer on the first conductive material to provide an etch stop capping layer on the first conductive material, wherein the metal oxide layer comprises an aluminum-based oxide or a cobalt-based oxide.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chu Wei-Chen
• Yang Tai-I
• Chuang Cheng-Chi
• Wu Chia-Tien

Classifications

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title