Display apparatus and method of driving the same

Patent metadata

Field	Value
Publication number	US-2018166010-A1
Application number	US-201715645567-A
Country	US
Kind code	A1
Filing date	Jul 10, 2017
Priority date	Dec 13, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

A display apparatus includes a plurality of pixels. Each pixel includes a first capacitor connected between a first voltage line receiving a driving signal and a first node; a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal, and a second electrode connected to a second node; an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal; a second capacitor connected between an m-th data line and the second node; a second transistor comprising a control electrode connected to an n-th gate line, a first electrode connected to the first node, and a second electrode connected to the second node;
and a third transistor comprising a control electrode connected to an n-th scan line, a first electrode connected to the first voltage line, and a second electrode connected to the second node.

First claim

What is claimed is:

1 . A display apparatus comprising:
a gate driver; a scan driver; and a display part comprising a plurality of pixels, each pixel including a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and an organic light emitting diode, wherein: the first capacitor is connected between a first voltage line receiving a driving signal and a first node, the first transistor comprises a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal, and a second electrode connected to a second node, the organic light emitting diode comprises an anode electrode connected to the second node and a cathode electrode receiving a second power source signal, the second capacitor is connected between an m-th data line and the second node, the second transistor comprises a control electrode connected to an n-th gate line, a first electrode connected to the first node, and a second electrode connected to the second node, the third transistor comprises a control electrode connected to an n-th scan line, a first electrode connected to the first voltage line, and a second electrode connected to the second node, the gate driver is configured to provide a plurality of gate lines in the display part with a gate signal including a first level voltage and a second level voltage, and the gate driver is configured to provide the n-th gate line with the first level voltage of the gate signal during an n-th horizontal period of a frame, and the scan driver is configured to provide a plurality of scan lines in the display part with a scan signal including a first level voltage and a second level voltage, and the scan driver is configured to provide the n-th scan line with the first level voltage of the scan signal during a first reset period of the frame prior to the n-th horizontal period of the frame.

2 . The display apparatus of claim 1 , wherein during a first period of the frame,
the first voltage line is configured to receive a second level voltage of the driving signal, the second voltage line is configured to receive a first level voltage of the first power source signal, the plurality of gate lines is configured to receive the first level voltage of the gate signal turning on the second transistor of the plurality of pixels, simultaneously, and the plurality of scan lines is configured to receive the first level voltage of the scan signal turning on the third transistor of the plurality of pixels, simultaneously.

3 . The display apparatus of claim 2 , wherein during a second period of the frame,
the first voltage line is configured to receive the second level voltage of the driving signal during an early part of the second period and to receive a reset voltage that is different from the second level voltage of the driving signal during a latter part of the second period, the second voltage line is configured to receive a second level voltage of the first power source signal, the plurality of gate lines is configured to receive the first level voltage of the gate signal turning on the second transistor of the plurality of pixels, simultaneously, and the plurality of scan lines is configured to receive the second level voltage of the scan signal turning off the third transistor of the plurality of pixels, simultaneously.

4 . The display apparatus of claim 3 , wherein the second level voltage of the first power source signal is lower than the second level voltage of the driving signal.

5 . The display apparatus of claim 3 , wherein a third period of the frame comprises the first reset period in which the first voltage line is configured to receive the reset voltage, the n-th scan line is configured to receive the first level voltage of the scan signal, and the n-th gate line is configured to receive the second level voltage of the gate signal turning off the second transistor.

6 . The display apparatus of claim 5 , wherein the first reset period comprises at least one horizontal period.

7 . The display apparatus of claim 5 , wherein the third period of the frame comprises a first holding period prior to the first reset period in which the first voltage line is configured to receive the reset voltage, the n-th scan line is configured to receive the second level voltage of the scan signal, and the n-th gate line is configured to receive the second level voltage of the gate signal.

8 . The display apparatus of claim 7 , wherein the third period of the frame further comprises a writing period corresponding to the n-th horizontal period after the first reset period in which the first voltage line is configured to receive the reset voltage, the n-th scan line is configured to receive the second level voltage of the scan signal, the n-th gate line is configured to receive the first level voltage of the gate signal, and the m-th data line is configured to receive a data voltage.

9 . The display apparatus of claim 8 , wherein during the n-th horizontal period, the first and second capacitors are connected to each other in series, the data voltage is divided by the first and second capacitors, and a divided data voltage is applied to the first node.

10 . The display apparatus of claim 8 , wherein the third period of the frame further comprises a second holding period placed after the writing period in which the first voltage line is configured to receive the reset voltage, the n-th scan line is configured to receive the second level voltage of the scan signal, and the n-th gate line is configured to receive the second level voltage of the gate signal.

11 . The display apparatus of claim 10 , wherein during the third period, the second voltage line is configured to receive the first level voltage of the first power source signal.

12 . The display apparatus of claim 10 , wherein during a fourth period of the frame, the first voltage line is configured to receive a first level voltage of the driving signal that is higher than the second level voltage of the driving signal, the second voltage line is configured to receive the first level voltage of the first power source signal, the plurality of gate lines is configured to receive the second level voltage of the gate signal, simultaneously, and the plurality of scan lines is configured to receive the second level voltage of the scan signal, simultaneously, and
wherein the first transistor is turned on by a difference voltage between the first and second level voltages of the driving signal, and a driving current corresponding to a data voltage applied to the first node flows in the organic light emitting diode.

13 . The display apparatus of claim 12 , wherein the frame further comprises a second reset period placed between the second holding period and the fourth period in which the first voltage line is configured to receive the reset voltage, the plurality of scan lines corresponding to a plurality of horizontal lines is configured to receive the first level voltage of the scan signal, simultaneously, and the plurality of gate signals is configured to receive the second level voltage of the gate signal, simultaneously.

14 . The display apparatus of claim 10 , wherein during the third period of the frame, the second voltage line is configured to receive a middle voltage between the first and second level voltages of the first power source signal.

15 . A method of driving a display apparatus that comprises a pixel circuit driving an organic light emitting diode, the method comprising:
applying a second level voltage of a drivin

Assignees

• Samsung Display Co Ltd

Inventors

• Park Jun-Hyun
• Lee An-Su
• Chung Bo-Yong
• Chai Chong-Chul

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2330/02

  Details of power systems and of start or stop of display operation · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G3/3258 Primary

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title