Semiconductor structure

Patent metadata

Field	Value
Publication number	US-2018158950-A1
Application number	US-201615371293-A
Country	US
Kind code	A1
Filing date	Dec 7, 2016
Priority date	Dec 7, 2016
Publication date	Jun 7, 2018
Grant date	—

Abstract

A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a first source/drain region having a first conductive type; a second source/drain region disposed opposite to the first source/drain region, the second source/drain region having the first conductive type; a channel doping region disposed between the first source/drain region and the second source/drain region, the channel doping region having the first conductive type; a gate structure disposed on the channel doping region; a first well having a first portion disposed under the first source/drain region, the first well having a second conductive type different from the first conductive type; and a second well disposed opposite to the first well and separated from the second source/drain region, the second well having the second conductive type.

2 . The semiconductor structure according to claim 1 , further comprising:
a first isolation structure; and a second isolation structure disposed opposite to the first isolation structure; wherein the first source/drain region, the second source/drain region and the channel doping region are disposed between the first isolation structure and the second isolation structure, the first well has a second portion disposed under the first isolation structure, and the second well is disposed under the second isolation structure.

3 . The semiconductor structure according to claim 2 , wherein the second source/drain region protrudes into the second isolation structure.

4 . The semiconductor structure according to claim 1 , wherein the first portion of the first well directly contacts the first source/drain region.

5 . The semiconductor structure according to claim 1 , wherein a thickness of the first source/drain region is equal to a thickness of the first portion of the first well.

6 . The semiconductor structure according to claim 1 , wherein the second well completely exposes the second source/drain region.

7 . The semiconductor structure according to claim 1 , wherein the second source/drain region comprises a first region and a second region, the first region is on the second region, and a doping concentration of the first region is higher than a doping concentration of the second region.

8 . The semiconductor structure according to claim 1 , wherein a thickness of the first portion of the first well is larger than a thickness of the first source/drain region.

9 . The semiconductor structure according to claim 1 , wherein a thickness of the first source/drain region is larger than a thickness of the first portion of the first well.

10 . The semiconductor structure according to claim 1 , wherein the first source/drain region comprises a first region and a second region, the first region is located in an upper portion of the second region and directly contacts the channel doping region, and a doping concentration of the first region is higher than a doping concentration of the second region.

11 . The semiconductor structure according to claim 1 , wherein the channel doping region is separated from the first source/drain region.

12 . The semiconductor structure according to claim 1 , further comprising:
a first source/drain contact disposed in the first source/drain region, the first source/drain contact having the first conductive type, wherein a doping concentration of the first source/drain contact is higher than a doping concentration of the first source/drain region; and a second source/drain contact disposed in the second source/drain region, the second source/drain contact having the first conductive type, wherein a doping concentration of the second source/drain contact is higher than a doping concentration of the second source/drain region.

13 . The semiconductor structure according to claim 1 , further comprising:
an intrinsic region, wherein the first source/drain region, the second source/drain region, the channel doping region, the first well and the second well are disposed in and directly contact the intrinsic region.

14 . The semiconductor structure according to claim 1 , wherein the first conductive type is n-type, and the second conductive type is p-type.

15 . The semiconductor structure according to claim 1 , wherein the first conductive type is p-type, and the second conductive type is n-type.

16 . The semiconductor structure according to claim 1 , wherein the first source/drain region is a drain region, and the second source/drain region is a source region.

17 . The semiconductor structure according to claim 1 , wherein the first source/drain region is a source region, and the second source/drain region is a drain region.

18 . The semiconductor structure according to claim 1 , comprising a depletion-type MOSFET including the first source/drain region, the second source/drain region, the channel doping region, the gate structure and the first well.

19 . The semiconductor structure according to claim 18 , wherein the depletion-type MOSFET has a minus threshold voltage.

20 . The semiconductor structure according to claim 18 , having a cell region and a periphery region, wherein the semiconductor structure comprises:
a word line coupled to memory cells disposed in the cell region; and a switch disposed in the cell region, the switch coupled to the word line, the switch comprising the depletion-type MOSFET.

Assignees

• Macronix Int Co Ltd

Inventors

• Chen Yung-Hsiang
• Chang Yao-Wen
• Liu Chu-Yung
• Yang I-Chen
• Chang Hsin-Wen

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H01L29/0847

  Electricity · mapped topic

• H01L27/11286

  Electricity · mapped topic

• H01L29/1083

  Electricity · mapped topic

• H01L29/7838 Primary

  Electricity · mapped topic