Magnetoresistive element and memory circuit

Patent metadata

Field	Value
Publication number	US-2018158496-A1
Application number	US-201615578377-A
Country	US
Kind code	A1
Filing date	May 31, 2016
Priority date	Jun 3, 2015
Publication date	Jun 7, 2018
Grant date	—

Abstract

A magnetoresistive element includes: a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a first ferromagnetic layer; a thin film that is located between the pin layer and the free layer; a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer and applies a pressure to the magnetostrictive layer; and an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer.

First claim

1 . A magnetoresistive element comprising:
a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a first ferromagnetic layer; a thin film that is located between the pin layer and the free layer; a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer and applies a pressure to the magnetostrictive layer; and an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer.

2 . The magnetoresistive element according to claim 1 , wherein
the electrode is located so as to surround at least a part of the piezoelectric substance, and the piezoelectric substance is dielectrically polarized in a direction from the magnetostrictive layer to the electrode or a direction from the electrode to the magnetostrictive layer.

3 . The magnetoresistive element according to claim 1 , wherein
the electrode includes a first electrode and a second electrode located at both sides in the stacking direction with respect to the piezoelectric substance, and the piezoelectric substance is (dielectrically polarized in the stacking direction.

4 . The magnetoresistive element according to claim 2 , wherein
when a polarity of a voltage applied to the pin layer with respect to the free layer reverses, a polarity of a voltage applied to the electrode with respect to the free layer does not change.

5 . The magnetoresistive element according to claim 3 , wherein
when a polarity of a voltage applied to the pin layer with respect to the free layer reverses, a polarity of a voltage applied to the second electrode with respect to the first electrode does not change.

6 . The magnetoresistive element according to claim 1 , wherein
the free layer includes a second ferromagnetic layer magnetically coupled to the magnetostrictive layer.

7 . The magnetoresistive element according to claim 1 , wherein
the magnetostrictive layer changes a direction of a magnetization easy axis thereof by application of pressure and reverses a magnetization direction of the free layer.

8 . The magnetoresistive element according to claim 7 , wherein
the magnetization direction of the free layer is reversed by spin-transfer-torque current-induced magnetization switching when the direction of the magnetization easy axis of the magnetostrictive layer changes.

9 . The magnetoresistive element according to claim 1 , wherein the thin film includes a tunnel barrier insulating layer or a non-magnetic metal layer.

10 . The magnetoresistive element according to claim 1 , wherein
the thin film includes a piezoresistor and the piezoelectric substance applies a pressure to the piezoresistor.

11 . A memory circuit comprising:
the magnetoresistive element according to claim 9 ; a bit line to which one of the free layer and the pin layer is coupled; a switch coupled to another of the free layer and the pin layer; a source line coupled to the another of the free layer and the pin layer through the switch; a word line to which a control terminal controlling the switch is coupled; and a control line to which the electrode is coupled.

12 . A memory circuit by comprising:
the magnetoresistive element according to claim 10 ; a bit line to which one of the free layer and the pin layer is coupled; a source line coupled to another of the free layer and the pin layer: and a word line coupled to the electrode.

13 . A memory circuit comprising:
a magnetoresistive element including:
a free layer that includes a magnetostrictive layer containing a magnetostrictive material;
a pin layer that includes a first ferromagnetic layer;
a thin film that is located between the pin layer and the free layer;
a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer, and applies a pressure to the magnetostrictive layer; and
an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer, and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer; and
a transistor including:
a source and a drain, one of the source and the drain being coupled to one of the free layer and the pin layer;
a channel that is located between the source and the drain and through which a carrier conducts from the source to the drain; and
a gate that surrounds at least a part of the channel from the intersecting direction, wherein
the source, the channel, and the drain are stacked in the stacking direction.

14 . The memory circuit according to claim 13 , wherein
the channel is a piezoresistor, and the gate includes a piezoelectric substance that applies a pressure to the channel from a direction intersecting with a direction in which the carrier conducts.

Assignees

• Japan Science & Tech Agency

Inventors

• Sugahara Satoshi
• Takamura Yota
• Nakagawa Shigeki

Classifications

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/14

  using thin-film elements · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title