Method and system for clock and data recovery (cdr)

Patent metadata

Field	Value
Publication number	US-2018152285-A1
Application number	US-201615385168-A
Country	US
Kind code	A1
Filing date	Dec 20, 2016
Priority date	Nov 29, 2016
Publication date	May 31, 2018
Grant date	—

Abstract

A clock and data recovery (CDR) device is disclosed. The CDR device comprises a sensing unit and an interpolator. The sensing unit is configured to detect a data center, a left data edge and a right data edge of a data on a data stream in a communication system, using a set of thresholds, in response to a first clock signal for sampling the data center, a second clock signal for sampling the left data edge and a third clock signal for sampling the right data edge. Each of the thresholds is related to a different level among data levels of the data. The interpolator is configured to generate the first clock signal based on information on the data center, and generate the second clock signal and the third clock signal based on information on the left and right data edges.

First claim

What is claimed is:

1 . A clock and data recovery (CDR) device, comprising:
a sensing unit configured to detect a data center, a left data edge and a right data edge of a data on a data stream in a communication system, using a set of thresholds, in response to a first clock signal for sampling the data center, a second clock signal for sampling the left data edge and a third clock signal for sampling the right data edge, each of the thresholds being related to a different level among data levels of the data; and an interpolator configured to generate the first clock signal based on information on the data center, and generate the second clock signal and the third clock signal based on information on the left and right data edges.

2 . The CDR device according to claim 1 , wherein the sensing unit includes a first set of sense amplifiers to detect the data center of the data in response to the first clock signal.

3 . The CDR device according to claim 1 , wherein the sensing unit includes a second set of sense amplifiers to detect the left data edge of the data in response to the second clock signal.

4 . The CDR device according to claim 1 , wherein the sensing unit includes a third set of sense amplifiers to detect the right data edge of the data in response to the third clock signal.

5 . The CDR device according to claim 1 further comprising:
a processing unit configured to determine a first phase difference for the first clock signal, and determine, based on information on data edges, a second phase difference for the second clock signal and a third phase difference for the third clock signal.

6 . The CDR device according to claim 1 , wherein the communication system includes a four-level pulse amplitude modulation (PAM-4) system, and wherein the first threshold has a value between binary 11 and 10, the second threshold has a value between binary 10 and 01, and the third threshold has a value between binary 01 and 00.

7 . The CDR device according to claim 1 , wherein a phase angle of the second clock signal is a function of ϕ 1 and ϕ 2 , where ϕ 1 and ϕ 2 represent the first phase difference and the second phase difference, respectively.

8 . The CDR device according to claim 1 , wherein a phase angle of the third clock signal is a function of ϕ 1 and ϕ 3 , where ϕ 1 and ϕ 3 represent the first phase difference and the third phase difference, respectively.

9 . The CDR device according to claim 1 , wherein an eye opening of the data is (2ϕ 1 +ϕ 2 +ϕ 3 )/2π, where ϕ 1 , ϕ 2 and ϕ 3 represent the first phase difference, the second phase difference and the third phase difference, respectively.

10 . A method of clock and data recovery, comprising:
determining a number of thresholds for sampling data on a data stream in a communication system, each of the thresholds being related to a different level among data levels of the data; determining a first phase difference for phase alignment with a data center of the data; generating clock signals of different phases based on the first phase difference for sampling, using the thresholds, the data center and data edges of the data, thereby obtaining information on data edges; aligning the clock signal for sampling the data center with the data center; determining a second phase difference for phase alignment with a left data edge of the data, and a third phase difference for phase alignment with a right data edge of the data based on the information on data edges; and adjusting the clock signals for sampling the data edges based on the second and third phase differences.

11 . The method according to claim 10 , wherein the communication system includes a four-level pulse amplitude modulation (PAM-4) system, and wherein thresholds include a first threshold having a value between binary 11 and 10, a second threshold having a value between binary 10 and 01, and a third threshold having a value between binary 01 and 00.

12 . The method according to claim 10 , wherein generating clock signals includes:
generating a first clock signal for sampling the data center of the data; generating a second clock signal for sampling a left data edge of the data; and generating a third clock signal for sampling a right data edge of the data.

13 . The method according to claim 10 , wherein a phase angle of the second clock signal is a function of ϕ 1 and ϕ 2 , where ϕ 1 and ϕ 2 represent the first phase difference and the second phase difference, respectively.

14 . The method according to claim 10 , wherein a phase angle of the third clock signal is a function of ϕ 1 and ϕ 3 , where ϕ 1 and ϕ 3 represent the first phase difference and the third phase difference, respectively.

15 . The method according to claim 10 , wherein an eye opening of the data is (2ϕ 1 +ϕ 2 +ϕ 3 )/2π, where ϕ 1 , ϕ 2 and ϕ 3 represent the first phase difference, the second phase difference and the third phase difference, respectively.

16 . The method according to claim 13 , wherein adjusting the clock signals includes:
adjusting the second clock signal in phase by selectively adding the second phase difference when the second clock is determined as lagging the left data edge, and subtracting the second phase difference when the second clock is determined as leading the left data edge.

17 . The method according to claim 13 , wherein adjusting the clock signals includes:
adjusting the third clock signal in phase by selectively adding the third phase difference when the third clock is determined as lagging the right data edge, and subtracting the third phase difference when the third clock is determined as leading the right data edge.

18 . A method of clock and data recovery in an N-level pulse width modulation (PAM-4) system, the method comprising:
determining (N−1) thresholds for sampling a data on a data stream, each of the thresholds being related to a different level among data levels of the data; generating a first clock signal for sampling, using the thresholds, a data center of the data, thereby obtaining information on data center; generating a second clock signal for sampling, using the thresholds, a left data edge of the data, and generating a third clock signal for sampling, using the thresholds, a right data edge of the data, thereby obtaining information on left and right data edges; and determining transmission timing of the first, second and third clock signal based on the information on data center and the information on left and right data edges.

19 . The method according to claim 18 further comprising determining a data transition type based on the information on data center and the information on left and right data edges.

20 . The method according to claim 18 , wherein N equals 4, and wherein the thresholds include a first threshold having a value between binary 11 and 10, a second threshold having a value between binary 10 and 01, and a third threshold having a value between binary 01 and 00.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shih Yu-Nan

Classifications

• H04L7/04 Primary

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H04L7/0083

  taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks · CPC title

• H04L7/0087 Primary

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/0025

  interpolation of clock signal · CPC title