Method And Apparatus For Memory Power And/Or Area Reduction

Patent metadata

Field	Value
Publication number	US-2018151202-A1
Application number	US-201815880913-A
Country	US
Kind code	A1
Filing date	Jan 26, 2018
Priority date	May 17, 2011
Publication date	May 31, 2018
Grant date	—

Abstract

A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage V mem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

First claim

What is claimed is:

1 . A method comprising:
in an electronic device comprising a power supply, digital circuitry, and a memory cell:
powering said digital circuitry via a first supply voltage generated by said power supply;
powering said memory cell via a second supply voltage generated by said power supply;
controlling said first supply voltage, using said power supply, independently of said second supply voltage; and
adjusting said second supply voltage, using said power supply, based on a type of data stored in said memory cell.

2 . The method of claim 1 , wherein a first type of data adheres to a first communication standard and a second type of data adheres to a second communication standard and said first and second communication standards control how received signals are processed to be transmitted from and received by said electronic device.

3 . The method of claim 2 , wherein said first type of data is of a first format and said second type of data is of a second format.

4 . The method of claim 1 , wherein said power supply adjusts said second supply voltage based on a tolerable error rate for data stored in said memory cell.

5 . The method of claim 1 , comprising powering a second memory cell via a third supply voltage generated by said power supply.

6 . The method of claim 5 , comprising controlling said third supply voltage, using said power supply, independently of said second supply voltage and independent of said first supply voltage.

7 . The method of claim 5 , wherein:
said memory cell holds a corresponding one or more most significant bits of a data word; and said second memory cell holds a corresponding one or more least significant bits of said data word.

8 . The method of claim 7 , wherein cell size of said memory cell is the same as cell size of said second memory cell.

9 . The method of claim 8 , wherein said second supply voltage is higher than said third supply voltage.

10 . The method of claim 7 , wherein cell size of said memory cell is larger than cell size of said second memory cell.

11 . The method of claim 10 , wherein said second supply voltage is equal to said third supply voltage.

12 . The method of claim 5 , wherein:
said memory cell holds a corresponding one or more bits of a data word having a first fault sensitivity coefficient; and said second memory cell holds a corresponding one or more bits of said data word having a second fault sensitivity coefficient.

13 . The method of claim 12 , wherein cell size of said memory cell is the same as cell size of said second memory cell.

14 . The method of claim 13 , wherein said second supply voltage is higher than said third supply voltage.

15 . The method of claim 12 , wherein cell size of said memory cell is larger than cell size of said second memory cell.

16 . The method of claim 9 , wherein said second supply voltage is equal to said third supply voltage.

17 . The method of claim 1 , wherein said memory cell comprises cross-coupled inverters.

18 . The method of claim 17 , wherein said first supply voltage is applied to source nodes of PMOS transistors of said cross-coupled inverters.

19 . The method of claim 1 , wherein said adjustment results in said second supply voltage being a first voltage when a first type of data is stored in said memory cell and said second supply voltage being a second voltage when a second type of data is stored in said memory cell.

20 . The method of claim 1 wherein said second supply voltage is applied to a source node of one or more access transistors that provide power to said memory cell.

Assignees

• Maxlinear Inc

Inventors

• Ling Curtis
• Smolyakov Vadim
• Gallagher Timothy
• Gulak Glenn

Classifications

• G11C2029/0409

  Online test · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C5/144 Primary

  Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title