Generating a unique die identifier for an electronic chip

Patent metadata

Field	Value
Publication number	US-2018149696-A1
Application number	US-201715808061-A
Country	US
Kind code	A1
Filing date	Nov 9, 2017
Priority date	Nov 30, 2016
Publication date	May 31, 2018
Grant date	—

Abstract

Generating a unique die identifier for an electronic chip including placing the electronic chip in an identifier generation state, wherein the electronic chip comprises a set of test circuits, wherein each of the set of test circuits is attached to a corresponding component on the electronic chip; obtaining an ordered list of race pairs of the set of test circuits; for each race pair in the ordered list of race pairs of the set of test circuits: selecting the race pair of test circuits; executing a race between the selected race pair; and adding an element to the unique die identifier based on an outcome of the executed race; and returning the electronic chip to an operational state.

First claim

1 . A method of generating a unique die identifier for an electronic chip, the method comprising:
placing the electronic chip in an identifier generation state, wherein the electronic chip comprises a set of test circuits, and wherein each of the set of test circuits is attached to a corresponding component on the electronic chip, wherein each of the corresponding components comprises a component utilized for primary operation of the electronic chip when the electronic chip is in an operational state; obtaining an ordered list of race pairs of the set of test circuits; for each race pair in the ordered list of race pairs of the set of test circuits:
executing a race between a race pair of the ordered list of race pairs, wherein each test circuit of the race pair is configured to utilize the corresponding component attached to the test circuit to execute the race; and
adding an element to the unique die identifier based on an outcome of the executed race; and
returning the electronic chip to an operational state.

2 . The method of claim 1 , wherein each of the corresponding components on the electronic chip is a capacitor, and wherein returning the electronic chip to the operational state comprises:
enabling each capacitor as a decoupling capacitor on the electronic chip.

3 . The method of claim 1 , further comprising:
storing the generated unique die identifier on the electronic chip.

4 . The method of claim 1 , wherein executing the race between a race pair of the ordered list of race pairs comprises:
transmitting a strobe signal simultaneously to each test circuit; and receiving, in response to the strobe signal, a response signal from each test circuit.

5 . The method of claim 1 , wherein the outcome of the executed race is determined based on the relative strength of corresponding field-effect transistors within the test circuits.

6 . The method of claim 1 , wherein placing the electronic chip in an identifier generation state comprises placing a portion of the electronic chip in a dormant state.

7 . The method of claim 1 , wherein selecting the race of the test circuits comprises:
sending a selection signal to each of the test circuits of the race pair, wherein the selection signal enables the test circuits to receive a strobe signal.

8 . An electronic chip that generates a unique die identifier, the electronic chip having disposed within it logic that causes the electronic chip to carry out the steps of:
placing the electronic chip in an identifier generation state, wherein the electronic chip comprises a set of test circuits, and wherein each of the set of test circuits is attached to a corresponding component on the electronic chip, wherein each of the corresponding components comprises a component utilized for primary operation of the electronic chip when the electronic chip is in an operational state; obtaining an ordered list of race pairs of the set of test circuits; for each race pair in the ordered list of race pairs of the set of test circuits:
selecting the race pair of test circuits;
executing a race between a race pair of the ordered list of race pairs, wherein each test circuit of the selected race pair is configured to utilize the corresponding component attached to the test circuit to execute the race; and
adding an element to the unique die identifier based on an outcome of the executed race; and
returning the electronic chip to an operational state.

9 . The electronic chip of claim 8 , wherein each of the corresponding components on the electronic chip is a capacitor, and wherein returning the electronic chip to the operational state comprises:
enabling each capacitor as a decoupling capacitor on the electronic chip.

10 . The electronic chip of claim 8 , the steps further comprising:
storing the generated unique die identifier on the electronic chip.

11 . The electronic chip of claim 8 , wherein executing the race between a race pair of the ordered list of race pairs comprises:
transmitting a strobe signal simultaneously to each test circuit; and receiving, in response to the strobe signal, a response signal from each test circuit.

12 . The electronic chip of claim 8 , wherein the outcome of the executed race is determined based on the relative strength of corresponding field-effect transistors within the test circuits.

13 . The electronic chip of claim 8 , wherein placing the electronic chip in an identifier generation state comprises placing a portion of the electronic chip in a dormant state.

14 . The electronic chip of claim 8 , wherein selecting the race of the test circuits comprises:
sending a selection signal to each of the test circuits of the race pair, wherein the selection signal enables the test circuits to receive a strobe signal.

15 . A computer program product for generating a unique die identifier for an electronic chip, the computer program product disposed upon the electronic chip, the computer program product comprising computer program instructions that, when executed, cause the electronic chip to carry out the steps of:
placing the electronic chip in an identifier generation state, wherein the electronic chip comprises a set of test circuits, and wherein each of the set of test circuits is attached to a corresponding component on the electronic chip, wherein each of the corresponding components comprises a component utilized for primary operation of the electronic chip when the electronic chip is in an operational state; obtaining an ordered list of race pairs of the set of test circuits; for each race pair in the ordered list of race pairs of the set of test circuits:
selecting the race pair of test circuits;
executing a race between a race pair of the ordered list of race pairs, wherein each test circuit of the selected race pair is configured to utilize the corresponding component attached to the test circuit to execute the race; and
adding an element to the unique die identifier based on an outcome of the executed race; and
returning the electronic chip to an operational state.

16 . The computer program product of claim 15 , wherein each of the corresponding components on the electronic chip is a capacitor, and wherein returning the electronic chip to the operational state comprises:
enabling each capacitor as a decoupling capacitor on the electronic chip.

17 . The computer program product of claim 15 , the steps further comprising:
storing the generated unique die identifier on the electronic chip.

18 . The computer program product of claim 15 , wherein executing the race between a race pair of the ordered list of race pairs comprises:
transmitting a strobe signal simultaneously to each test circuit; and receiving, in response to the strobe signal, a response signal from each test circuit.

19 . The computer program product of claim 15 , wherein placing the electronic chip in an identifier generation state comprises placing a portion of the electronic chip in a dormant state.

20 . The computer program product of claim 15 , wherein selecting the race of the test circuits comprises:
sending a selection signal to each of the test circuits of the race pair, wherein the selection signal enables the test circuits to receive a strobe signal.

Assignees

• IBM

Inventors

• Erickson Karl R
• Paone Phil C
• Paulsen David P
• Sheets Ii John E
• Uhlmann Gregory J

Classifications

• H03K19/17792

  for operating speed · CPC title

• H03K19/17744 Primary

  for input/output signals · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title