Power-good detector for ultra-wide band transmitter with emphasis on low power consumption

Patent metadata

Field	Value
Publication number	US-2018145706-A1
Application number	US-201615570108-A
Country	US
Kind code	A1
Filing date	Apr 28, 2016
Priority date	Apr 30, 2015
Publication date	May 24, 2018
Grant date	—

Abstract

Systems, devices and methods are disclosed using a transmitter architecture to keep the transmitter in a deep sleep mode before activation/enabling. The transmitter tag comprises a power-good-detector, a first regulator and a second regulator. The power-good-detector includes a power-good-latch, a ring oscillator and a ripple counter. Upon disconnecting a GPIO pin from the ground, the power-good-latch sends a Bias_EN signal to the regulator. Upon receipt of the Bias_EN signal, the first regulator transmits a wakeup signal to the ring oscillator, which then starts sending the clock signals to the ripple counter. When the counted clock signals reach a threshold value, the ripple counter sends the power-good-digital signal to the flip flops. When the tag is in the reset mode, the power-good-digital signal is also low. When the power-good-digital signal goes from low to high, the tag is out of the reset mode.

First claim

1 . An ultra-broad-band (UWB) transmitter tag comprising:
a latch coupled to ground via a pin, the latch sends a bias enabling signal and a reset count signal after the pin is disconnected from ground; a first regulator coupled to the latch, the first regulator receives the bias enabling signal and transmits a wakeup signal; an oscillator coupled to the first regulator, the oscillator receives the wakeup signal and sends at least one clock signal; and a counter coupled to the latch and the oscillator, the counter counts the at least one clock signal, when the at least one clock signal reaches a threshold value, the counter sends a signal to enable the UWB transmitter tag.

2 . The UWB transmitter tag of claim 1 further comprising a second regulator coupled to the latch, the second regulator receive the bias enabling signal and transmit a ripple-clock-output signal.

3 . The UWB transmitter tag of claim 2 further comprising at least one flip flop coupled to the counter and the second regulator, the at least one flip flop receives both the ripple-clock-output signal and the power-good-digital signal and generates a digital-reset-bar signal.

4 . The UWB transmitter tag of claim 3 wherein when the signal sent from the counter and the digital-reset-bar signal are low, the UWB transmitter tag is in a reset mode, wherein when the signal sent from the counter goes from low to high, the digital-reset-bar signal goes to high and indicates that the UWB transmitter tag is out of the reset mode.

5 . The UWB transmitter tag of claim 2 wherein the second regulator is a 1.8 V low-dropout (LDO) and relaxation oscillator.

6 . The UWB transmitter tag of claim 1 wherein the first regulator is a 1.2 V low-dropout (LDO) and bandgap oscillator.

7 . The UWB transmitter tag of claim 1 wherein the counter counts the at least one clock signal for a preset time interval.

8 . The UWB transmitter tag of claim 1 further comprising at least one delay circuit coupled to the counter to process the signal sent from the counter.

9 . A method of enabling an ultra-broad-band (UWB) transmitter tag comprising:
sending a bias enabling signal from a latch connected to ground via a pin when the pin is disconnected from ground; receiving, at a first regulator coupled to the latch, the bias enabling signal and transmitting a wakeup signal from the first regulator; receiving, at an oscillator, the wakeup signal and sending at least one clock signal from the oscillator; receiving and counting, at a counter, the at least one clock signal; and sending from the counter a signal to enable the UWB transmitter tag when the at least one clock signal reaches a threshold value.

10 . The method of claim 9 further comprising receiving, at a second regulator coupled to the latch, the bias enabling signal and transmit a ripple-clock-output signal from the second regulator.

11 . The method of claim 10 further comprising receiving both the ripple-clock-output signal and the signal sent from the counter, at a flip flop coupled to both the counter and the second regulator, and generating a digital-reset-bar signal from the flip flop.

12 . The method of claim 9 wherein the at least one clock signal is counted within a preset time interval.

13 . The method of claim 9 further comprising pulling down the pin using a weak pull down signal after a time interval when the signal sent from the counter is high.

14 . The method of claim 13 wherein the weak pull down signal indicates that the UWB transmitter tag is enabled completely.

15 . A detector for enabling an ultra-broad-band (UWB) transmitter tag comprising:
a pin coupled to ground, the disconnection of the pin from the ground enabling an enabling pulse signal; an oscillator and a counter receiving the enabling pulse signal and sending a pulse signal; an R-latch coupled to the oscillator and the counter, the R-latch receives the enabling pulse signal and the pulse signal from the counter and transmits an interrupt signal; and a logic gate receiving the pulse signal and the interrupt signal to output a bias enabling signal for UWB transmitter tag enabling.

16 . The detector of claim 15 wherein the logic gate is an OR-gate.

17 . The detector of claim 15 further comprising at least one delay circuit coupled to the R-latch to process the interrupt signal and generate an out signal for UWB transmitter tag enabling.

18 . The detector of claim 17 wherein the enabling pulse signal is the signal at a node coupled to a PMOS transistor and a low threshold NMOS transistor, the PMOS transistor coupled to a power source and the low threshold NMOS transistor coupled to ground.

19 . The detector of claim 15 wherein the R-latch receives the enabling pulse signal via an NMOS in deep N-well and receives the pulse signal via a metal-oxide-semiconductor field-effect transistor (MOSFET).

20 . The detector of claim 19 wherein the R-latch further comprises a leakage compensating unit coupled to the NMOS in deep N-well, the leakage compensating unit compensates current leakage through the NMOS in deep N-well.

Assignees

• Maxim Integrated Products

Inventors

• Muthali Harish S
• Pahlavan Kourosh
• Vauhkonen Ari

Classifications

• H04B1/0475 Primary

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H04B1/04 Primary

  Circuits · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• H04B1/7174

  Pulse generation (in general H04L25/03834) · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title