Data mapping scheme for generalized product codes

Patent metadata

Field	Value
Publication number	US-2018145705-A1
Application number	US-201615356069-A
Country	US
Kind code	A1
Filing date	Nov 18, 2016
Priority date	Nov 18, 2016
Publication date	May 24, 2018
Grant date	—

Abstract

Memory systems and operating methods thereof comprise a memory storage and an error control coding (ECC) unit. The memory storage stores data which is split into a plurality of data chunks. The error control coding (ECC) unit is suitable for arranging each data chunk into codewords, each data chunk is arranged as part of at least two codewords, and mapping the codewords by reverse indexing the data chunks.

First claim

1 . A memory system, comprising:
a memory storage including data split into a plurality of data chunks; and an error control coding (ECC) unit suitable for:
constructing codewords with the plurality of data chunks, wherein each of the data chunks is shared by at least two codewords; and
mapping the codewords with the data chunks by a multi-dimension mapping scheme of reverse indexing the data chunks, wherein mapping complexity of the multi-dimension mapping scheme is reduced to O(N) or less, and N is the number of data chucks in a single codeword.

2 . The memory system of claim 1 , wherein the reverse indexing includes at least a representation of indexing a data chunk location within a constituent codeword.

3 . The memory system of claim 1 , wherein the reverse indexing includes at least a representation of indexing a data chunk location within a general product code (GPC) codeword.

4 . The memory system of claim 1 , further comprising a lookup table (LUT).

5 . The memory system of claim 4 , wherein the ECC unit is further suitable for mapping the codewords by making computations for the reverse indexing using the LUT.

6 . The memory system of claim 1 , wherein the plurality of data chunks is split according to a general product code structure.

7 . A method, comprising:
constructing codewords with a plurality of data chunks, arranging, with an error control coding (ECC) unit, wherein each of the data chunks is shared by at least two codewords; and mapping the codewords with the data chunks a multi-dimension mapping scheme of by reverse indexing the data chunks, wherein mapping complexity of the multi-dimension mapping scheme is reduced to O(N) or less, and N is the number of data chucks in a single codeword.

8 . The method of claim 7 , wherein the reverse indexing includes at least a representation of indexing a data chunk location within a constituent codeword.

9 . The method of claim 7 , wherein the reverse indexing includes at least a representation of indexing a data chunk location within a general product code (GPC) codeword.

10 . The method of claim 7 , further comprising providing a lookup table (LUT).

11 . The method of claim 10 , further comprising mapping the codewords by making computations for the reverse indexing using the LUT.

12 . The method of claim 7 , wherein the plurality of data chunks is split according to a general product code structure.

13 . A memory device, comprising:
a memory storage including data split into a plurality of data chunks; and an error control coding (ECC) unit configured to:
constructing codewords with the plurality of data chunks, wherein each of the data chunks is shared by at least two codewords; and
map the codewords with the data chunks by a multi-dimension mapping scheme of reverse indexing the data chunks, wherein mapping complexity of the multi-dimension mapping scheme is reduced to O(N) or less, and N is the number of data chucks in a single codeword.

14 . The memory device of claim 13 , wherein the reverse indexing includes at least a representation of indexing a data chunk location within a constituent codeword.

15 . The memory device of claim 13 , wherein the reverse indexing includes at least a representation of indexing a data chunk location within a general product code (GPC) codeword.

16 . The memory device of claim 13 , further comprising a lookup table (LUT).

17 . The memory device of claim 16 , wherein the ECC unit is further configured to map the codewords by making computations for the reverse indexing using the LUT.

18 . The memory device of claim 13 , wherein the plurality of data chunks is split according to a general product code structure.

Assignees

• Sk Hynix Memory Solutions Inc

Inventors

• Lin Yi-Min
• Bhatia Aman
• Kumar Naveen
• Yen Johnson

Classifications

• G06F3/064

  Management of blocks · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• H03M13/2909 Primary

  Product codes · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title