Semiconductor device
US-2017033710-A1 · Feb 2, 2017 · US
Semiconductor module
US2018138828A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018138828-A1 |
| Application number | US-201815867978-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jan 11, 2018 |
| Priority date | Jul 31, 2015 |
| Publication date | May 17, 2018 |
| Grant date | — |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device comprising: a sealing body comprised of a quadrangle in plan view; a first lead group arranged along a first side of the sealing body in plan view; a second lead group arranged along a second side of the sealing body facing the first side in plan view; a first component mounting portion arranged between the first lead group and the second lead group in plan view; a plurality of second component mounting portions arranged between the first lead group and the second lead group, and arranged between the first component mounting portion and the second lead group in plan view; a first electronic component sealed with the sealing body, and mounted on the first component mounting portion; a substrate sealed with the sealing body, mounted on the first component mounting portion, and arranged adjacent to the first electronic component in plan view; and a plurality of second electronic components sealed with the sealing body, and respectively mounted on the plurality of second component mounting portions, wherein the plurality of second electronic components are arranged along the second side of the sealing body, wherein the first electronic component and a part of the first lead group are electrically connected with each other, wherein the first electronic component and each of the plurality of second electronic components are electrically connected with each other, wherein the second electronic component and a part of the second lead group are electrically connected with each other, and wherein the first electronic component and a part of the plurality of second electronic components are electrically connected with each other via a first wire coupling the first electronic component and the substrate, the substrate and a second wire coupling the substrate and the part of the plurality of second electronic components.
Assignees
Inventors
Classifications
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
between laterally-adjacent chips · CPC title
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
the semiconductor body being completely enclosed · CPC title
Encapsulations, e.g. protective coatings · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2018138828A1 cover?
- Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Simila…
- Who is the assignee on this patent?
- Renesas Electronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu May 17 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).