Methods of forming semiconductor devices using semi-bidirectional patterning

Patent metadata

Field	Value
Publication number	US-2018138187-A1
Application number	US-201715662594-A
Country	US
Kind code	A1
Filing date	Jul 28, 2017
Priority date	Nov 15, 2016
Publication date	May 17, 2018
Grant date	—

Abstract

Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first, a second, and a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.

First claim

What is claimed is:

1 . An intermediate semiconductor device comprising:
a dielectric layer; a first hardmask layer; a set of nitride lines periodically in a first direction approximately 15 nm to approximately 35 nm wide; and a set of connecting nitride lines in a second direction approximately 10 nm to approximately 30 nm wide, wherein a width of the set of connecting nitride lines is less than a width of the set of nitride lines.

2 . The device of claim 1 , wherein device comprises a logic device and the nitride lines are approximately 30 nm apart.

3 . The device of claim 2 , wherein the connecting nitride lines are approximately 36 nm apart from an adjacent connecting nitride line.

4 . The device of claim 1 , wherein the device comprises an SRAM cell.

5 . The device of claim 4 , wherein the nitride lines are approximately 64 nm apart.

6 . The device of claim 5 , wherein the connecting nitride lines are approximately 36 nm apart from an adjacent connecting nitride line.

Assignees

• Globalfoundries Inc

Inventors

• Ogino Atsushi

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H01L21/31144

  Electricity · mapped topic

• H01L21/0332

  Electricity · mapped topic