Semiconductor device and a method of increasing a resistance value of an electric fuse

Patent metadata

Field	Value
Publication number	US-2018138121-A1
Application number	US-201815869707-A
Country	US
Kind code	A1
Filing date	Jan 12, 2018
Priority date	Mar 7, 2006
Publication date	May 17, 2018
Grant date	—

Abstract

A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.

First claim

We claim:

1 . A semiconductor device, comprising:
a semiconductor substrate; an interlayer dielectric formed on the semiconductor substrate; a first insulating layer formed on the interlayer dielectric, and having a first trench; a barrier film formed on side and bottom surfaces of the first trench; an electric fuse formed on the barrier film in the first trench; a second insulating layer formed on the electric fuse and on the first insulating layer such that the second insulating layer directly contacts with the electric fuse; and a third insulating layer formed on the second insulating layer, wherein a linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and wherein a melting point of the barrier film is greater than a melting point of the electric fuse.

2 . The semiconductor device according to the claim 1 , wherein the electric fuse includes copper.

3 . The semiconductor device according to the claim 1 , further comprising a first wiring formed in a second trench formed in the first insulating layer,
wherein a width of the electric fuse is smaller than a width of the first wiring.

4 . The semiconductor device according to the claim 3 , wherein the electric fuse is comprised of a second wiring having both ends connected with the first wiring.

5 . The semiconductor device according to the claim 1 ,
wherein the second insulating layer includes first and second layers, wherein the first layer includes Si and O, and wherein the second layer includes Si, C and N.

6 . The semiconductor device according to the claim 1 , wherein the first insulating layer has a relative dielectric constant of 3 or less.

7 . The semiconductor device according to the claim 1 , further comprising;
a fourth insulating layer formed on the third insulating layer, and having a third trench; and a third wiring formed in the third trench, wherein a width of the third wiring is greater than a width of the first wiring.

8 . The semiconductor device according to the claim 1 , wherein the electric fuse is formed to be cut by applying an electrical current to the electric fuse.

9 . The semiconductor device according to claim 1 , wherein the barrier film includes Ta.

10 . The semiconductor device according to claim 2 , wherein the barrier film is located between the copper film and the side and bottom surfaces of the first trench.

11 . The semiconductor device according to claim 1 , wherein the barrier film includes first and second barrier films at the side surface of the first trench.

12 . The semiconductor device according to claim 11 , wherein the first barrier film includes Ta and the second barrier film includes TaN.

Assignees

• Renesas Electronics Corp

Inventors

• Iwamoto Takeshi
• Kono Kazushi
• Arakawa Masashi
• Yonezu Toshiaki
• Obayashi Shigeki

Classifications

• H10W42/80 Primary

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/49

  Adaptable interconnections, e.g. fuses or antifuses · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title