Memory system and operation method thereof

Patent metadata

Field	Value
Publication number	US-2018129565-A1
Application number	US-201715644132-A
Country	US
Kind code	A1
Filing date	Jul 7, 2017
Priority date	Nov 9, 2016
Publication date	May 10, 2018
Grant date	—

Abstract

The memory system includes a BCH error correction circuit suitable for generating a BCH error correction code using a first write data which is a portion of a write data from a host, a Hamming error correction circuit suitable for generating a Hamming error correction code using a second write data which is a remaining portion of the write data, a plurality of first memory devices suitable for storing first write data and the BCH error correction code, and one or more second memory devices suitable for storing the second write data and the Hamming error correction code.

First claim

What is claimed is:

1 . A memory system, comprising:
a BCH error correction circuit suitable for generating a BCH error correction code using a first write data which is a portion of a write data from a host; a Hamming error correction circuit suitable for generating a Hamming error correction code using a second write data which is a remaining portion of the write data; a plurality of first memory devices suitable for storing the first write data and the BCH error correction code; and one or more second memory devices suitable for storing the second write data and the Hamming error correction code.

2 . The memory system of claim 1 , wherein the second memory devices have a lower bit error rate (BER) than the first memory devices.

3 . The memory system of claim 1 ,
wherein a size of the write data is 512 bits, wherein a total size of the first write data and the BCH error correction code is less than or equal to 511 bits, and wherein a total size of the second write data and the Hamming error correction code is less than 64 bits.

4 . The memory system of claim 3 ,
wherein a size of the first write data is 457 bits, and wherein a size of the BCH error correction code is 54 bits.

5 . The memory system of claim 4 ,
wherein a size of the second write data is 55 bits, and wherein a size of the Hamming error correction code is 7 or 8 bits.

6 . The memory system of claim 1 ,
wherein the BCH error correction circuit further BCH ECC-decodes a first read data read from the first memory devices using the BCH error correction code read from the first memory devices, wherein the Hamming error correction circuit further Hamming ECC-decodes a second read data read from the second memory devices using the Hamming error correction code read from the second memory devices, and wherein the BCH ECC-decoded first read data and the Hamming ECC-decoded second data are provided to the host as a read data.

7 . The memory system of claim 1 ,
wherein the BCH error correction circuit and the Hamming error correction circuit are included in a memory controller, and wherein the first memory devices and the second memory devices are included in a memory module.

8 . A memory system, comprising:
a BCH error correction circuit suitable for generating a BCH error correction code using a first write data which is a portion of a 512-bit write data from a host; a Hamming error correction circuit suitable for generating a Hamming error correction code using a second write data which is the remaining portion of the 512-bit write data; eight first memory devices suitable for storing the first write data and the BCH error correction code; and a second memory device suitable for storing the second write data and the Hamming error correction code.

9 . The memory system of claim 8 , wherein the second memory device has a lower bit error rate (BER) than the first memory devices.

10 . The memory system of claim 8 ,
wherein a total size of the first write data and the BCH error correction code is less than or equal to 511 bits, and wherein a total size of the second write data and the Hamming error correction code is less than 64 bits.

11 . The memory system of claim 10 ,
wherein a size of the first data is 457 bits, wherein a size of the BCH error correction code is 54 bits, wherein a size of the second data is 55 bits, and wherein a size of the Hamming error correction code is 7 or 8 bits.

12 . The memory system of claim 8 ,
wherein the BCH error correction circuit further BCH ECC-decodes a first read data read from the first memory devices using the BCH error correction code read from the first memory devices, wherein the Hamming error correction circuit further Hamming ECC-decodes a second read data read from the second memory device using the Hamming error correction code read from the second memory device, and wherein the BCH ECC-decoded first read data and the Hamming ECC-decoded second read data are provided to the host as a 512-bit read data.

13 . The memory system of claim 8 ,
wherein the BCH error correction circuit and the Hamming error correction circuit are included in a memory controller, and wherein the first memory devices and the second memory device are included in a memory module.

14 . A memory system, comprising:
a memory controller including a first-type error correction circuit suitable for generating a first error correction code using a first write data which is a portion of a write data form a host, and a second-type error correction circuit suitable for generating a second error correction code using a second write data which is the remaining portion of the write data, wherein error correction algorithms used by the first-type error correction circuit and the second-type error correction circuit are different from each other; and a memory module including a plurality of first memory devices suitable for storing the first write data and the first error correction code, and one or more second memory device suitable for storing the second write data and the second error correction code.

15 . The memory system of claim 14 ,
wherein the first-type error correction circuit uses a BCH error correction algorithm, and wherein the second-type error correction circuit uses a Hamming error correction algorithm.

16 . The memory system of claim 15 , wherein the second memory device has a lower bit error rate (BER) than the first memory devices.

17 . The memory system of claim 15 ,
wherein a size of the write data is 512 bits, wherein a total size of the first write data and the first error correction code is less than or equal to 511 bits, and wherein a total size of the second write data and the second error correction code is less than 64 bits.

18 . The memory system of claim 17 ,
wherein a size of the first write data is 457 bits, and wherein a size of the first error correction code is 54 bits.

19 . The memory system of claim 18 ,
wherein a size of the second write data is 55 bits, and wherein a size of the second error correction code is 7 or 8 bits.

20 . The memory system of claim 14 , wherein the memory module includes eighteen memory devices, where fourteen memory devices are configured to receive the first write data and four memory devices are configured to receive the second write data.

Assignees

• Sk Hynix Inc

Inventors

• Lee Sung-Eun
• Kwon Jung-Hyun
• JO Sang-Gu

Classifications

• H03M13/19

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• H03M13/2906

  using block codes (H03M13/2957 takes precedence) · CPC title

• H03M13/152

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title