Rsa decryption processor and method for controlling rsa decryption processor

Patent metadata

Field	Value
Publication number	US-2018123792-A1
Application number	US-201715619151-A
Country	US
Kind code	A1
Filing date	Jun 9, 2017
Priority date	Nov 1, 2016
Publication date	May 3, 2018
Grant date	—

Abstract

The present application discloses an RSA decryption processor and a method for controlling an RSA decryption processor. A specific implementation of the processor includes a memory, a control component, and a parallel processor. The memory is configured to store decryption parameters comprising a private key. The control component is configured to receive a ciphertext set, and send a decryption signal comprising the ciphertext set to the parallel processor. The parallel processor is configured to: read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts. This implementation improves the efficiency of RSA decryption.

First claim

What is claimed is:

1 . An RSA decryption processor, comprising a memory, a control component, and a parallel processor, wherein
the memory is configured to store decryption parameters comprising a private key; the control component is configured to receive a ciphertext set, and send a decryption signal comprising the ciphertext set to the parallel processor; and the parallel processor is configured to: read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts.

2 . The RSA decryption processor according to claim 1 , further comprising a preprocessing circuit unit, wherein the decryption parameters further comprise a preset first factor and second factor prime with each other;
the control component is further configured to send a preprocessing signal comprising the ciphertext set to the preprocessing circuit unit, in response to that a ciphertext bit width of the ciphertext set is greater than a predetermined threshold; the preprocessing circuit unit is configured to: read a decryption parameter from the memory in response to receiving the preprocessing signal, and perform an operation on the decryption parameter and a ciphertext whose bit width is greater than the predetermined threshold in the ciphertext set according to the Chinese remainder theorem, to determine intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold, wherein the intermediate parameters comprise a first base, a first exponent, a second base, and a second exponent; and the control component is further configured to: monitor the preprocessing circuit unit, and determine whether a modular exponentiation circuit unit in the parallel processor is idle, in response to detecting that the preprocessing circuit unit completes determining the intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold.

3 . The RSA decryption processor according to claim 2 , wherein
the control component is further configured to: send a first task transfer instruction to the preprocessing circuit unit and the idle modular exponentiation circuit unit, in response to determining that an modular exponentiation circuit unit in the parallel processor is idle; the preprocessing circuit unit is further configured to: send the determined intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold to the idle modular exponentiation circuit unit, in response to receiving the first task transfer instruction; and the idle modular exponentiation circuit unit is further configured to: receive the intermediate parameters sent from the preprocessing circuit unit in response to receiving the first task transfer instruction, and perform a first modular exponentiation operation on the received first base, first exponent, and first factor and perform a second modular exponentiation operation on the received second base, second exponent, and second factor, to determine a first remainder and a second remainder.

4 . The RSA decryption processor according to claim 3 , further comprising a post-processing circuit unit, wherein
the control component is further configured to: monitor the modular exponentiation circuit unit in the parallel processor, determine whether the post-processing circuit unit is idle in response to detecting that a modular exponentiation circuit unit in the parallel processor has determined the first remainder and the second remainder, and send a second task transfer instruction to the parallel processor and the post-processing circuit unit in response to determining that the post-processing circuit unit is idle; the parallel processor is further configured to: send the determined first remainder and second remainder, the first factor, and the second factor to the post-processing circuit unit in response to receiving the second task transfer instruction; and the post-processing circuit unit is configured to: perform an operation on the first remainder, the second remainder, the first factor, and the second factor according to the Chinese remainder theorem to determine a plaintext corresponding to the ciphertext whose bit width is greater than the predetermined threshold, in response to receiving the second task transfer instruction, the first remainder, the second remainder, the first factor, and the second factor.

5 . The RSA decryption processor according to claim 1 , wherein the modular exponentiation circuit unit receiving the intermediate parameters comprises a first modular exponentiation subunit and a second modular exponentiation subunit in parallel,
the first modular exponentiation subunit is configured to perform a first modular exponentiation operation on the first base, the first exponent, and the first factor, to determine the first remainder; and the second modular exponentiation subunit is configured to perform a second modular exponentiation operation on the second base, the second exponent, and the second factor, to determine the second remainder.

6 . The RSA decryption processor according to claim 5 , wherein the first modular exponentiation subunit comprises a first modular exponentiation control subunit and a first pulse array circuit unit,
the first pulse array circuit unit is configured to perform a modular multiplication operation; and the first modular exponentiation control subunit is configured to: call the first pulse array circuit unit at least once to perform a modular multiplication operation according to the first base, the first exponent, and the first factor, so as to complete the first modular exponentiation operation to determine the first remainder.

7 . The RSA decryption processor according to claim 6 , wherein the second modular exponentiation subunit comprises a second modular exponentiation control subunit and a second pulse array circuit unit,
the second pulse array circuit unit is configured to perform a modular multiplication operation; and the second modular exponentiation control subunit is configured to: call the second pulse array circuit unit at least once to perform a modular multiplication operation according to the second base, the second exponent, and the second factor, so as to complete the second modular exponentiation operation to determine the second remainder.

8 . The RSA decryption processor according to claim 7 , wherein
each of the first pulse array circuit unit and the second pulse array circuit unit comprises a predetermined number of multiply-add operation units; and the modular exponentiation circuit unit receiving the intermediate parameters is further configured to: calculate a ratio of the number of multiply-add operation units in the first pulse array circuit unit to the first factor to obtain a first ratio, calculate a ratio of the number of multiply-add operation units in the second pulse array circuit unit to the second factor to obtain a second ratio, and incorporate at least one multiply-add operation unit in the pulse array circuit unit corresponding to the greater ratio into the pulse array circuit unit corresponding to the smaller ratio, in response to that the first ratio is not equal to the second ratio.

9 . A method for controlling an RSA decryption processor, wherein the RSA decryption processor comprises a memory and a parallel processor, the memory is configured to store decryption parameters comprising a private key,

Assignees

• Beijing Baidu Netcom Sci & Tec

Inventors

• Tu Yichen
• Qi Wei
• Wang Yong

Classifications

• H04L9/302 Primary

  involving the integer factorization problem, e.g. RSA or quadratic sieve [QS] schemes · CPC title

• H04L9/0618

  Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation · CPC title

• H04L9/30 Primary

  Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L9/06

  the encryption apparatus using shift registers or memories for block-wise {or stream} coding, e.g. DES systems {or RC4; Hash functions; Pseudorandom sequence generators} · CPC title