Ethernet physical layer device having an integrated physical coding and forward error correction sub-layers

Patent metadata

Field	Value
Publication number	US-2018123733-A1
Application number	US-201615336974-A
Country	US
Kind code	A1
Filing date	Oct 28, 2016
Priority date	Oct 28, 2016
Publication date	May 3, 2018
Grant date	—

Abstract

Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.

First claim

What is claimed is:

1 . A physical layer device comprising:
a physical coding sub-layer; a forward error correction sub-layer; and an integration block in communication with and operably connected to the physical coding sub-layer and the forward error correction sub-layer, the integration block halting, for a number of clock cycles, a data stream in portions of a data path within the physical coding sub-layer and the forward error correction sub-layer so as to compensate for processing of the data stream by a data processor in a portion of the data path within the forward error correction sub-layer.

2 . The physical layer device of claim 1 , the integration block comprising:
processing compensation logic operably connected to clock compensation logic in a portion of the data path within the physical coding sub-layer; and a data path controller in communication with the data processor, the processing compensation logic and other components in the data path within both the physical coding sub-layer and the forward error correction sub-layer, the data path controller performing the following:
receiving a processing signal from the data processor;
based on the processing signal, determining the number of clock cycles during which the data stream in the data path is to be halted; and
generating and transmitting a data halt signal indicating the number of clock cycles to the processing compensation logic and the other components.

3 . The physical layer device of claim 2 , the processing compensation logic and the other components receiving the data halt signal from the data path controller and, in response to the data halt signal, halting all functions for the number of clock cycles indicated.

4 . The physical layer device of claim 1 , the data path being a transmitter data path and the data processor being a code word mark inserter that inserts code word marks into the data stream to allow for detection of data packet boundaries.

5 . The physical layer device of claim 1 , the data path being a receiver data path and the data processor being a code word mark remover that removes code word marks from the data stream.

6 . The physical layer device of claim 1 , wherein the physical layer device comprises at least one of a transmitter, a receiver and a transceiver.

7 . A physical layer transceiver comprising:
a physical coding sub-layer; a forward error correction sub-layer; and a pair of physical coding sub-layer and forward error correction sub-layer integration blocks comprising:
a first integration block in communication with and operably connected to the physical coding sub-layer and the forward error correction sub-layer, the first integration block halting, for a first number of clock cycles, a transmitter data stream in portions of a transmitter data path within the physical coding sub-layer and the forward error correction sub-layer so as to compensate for code word mark insertion into the transmitter data stream by a code word mark inserter, the code word mark inserter being in a portion of the transmitter data path within the forward error correction sub-layer; and,
a second integration block in communication with and operably connected to the physical coding sub-layer and the forward error correction sub-layer, the second integration block halting, for a second number of clock cycles, a receiver data stream in portions of a receiver data path within the physical coding sub-layer and the forward error correction sub-layer so as to compensate for code word mark removal from the receiver data stream by a code word mark remover, the code word mark remover being in a portion of the receiver data path with the forward error correction sub-layer.

8 . The physical layer transceiver of claim 7 , the first integration block comprising:
code word mark insertion compensation logic operably connected to transmitter clock compensation logic in a portion of the transmitter data path within the physical coding sub-layer; and a transmitter data path controller in communication with the code word mark inserter, the code word mark insertion compensation logic and other transmitter components in the transmitter data path within both the physical coding sub-layer and the forward error correction sub-layer, the transmitter data path controller performing the following:
receiving a code word mark insertion signal from the code word mark inserter;
based on the code word mark insertion signal, determining the first number of clock cycles during which the transmitter data stream is to be halted; and
generating and transmitting a transmitter data halt signal indicating the first number of clock cycles to the code word mark insertion compensation logic and the other transmitter components.

9 . The physical layer transceiver of claim 8 , the code word mark insertion compensation logic and the other transmitter components receiving the transmitter data halt signal from the transmitter data path controller and, in response to the transmitter data halt signal, halting all functions for the first number of clock cycles indicated.

10 . The physical layer transceiver of claim 8 , the code word mark inserter inserting code word marks into the transmitter data stream to allow for detection of data packet boundaries.

11 . The physical layer transceiver of claim 7 , the second integration block comprising:
code word mark removal compensation logic operably connected to receiver clock compensation logic in a portion of the receiver data path within the physical coding sub-layer; and a receiver data path controller in communication with the code word mark remover, the code word mark removal compensation logic, and other receiver components in the receiver data path within both the physical coding sub-layer and the forward error correction sub-layer, the receiver data path controller performing the following:
receiving a code word mark removal signal from the code word mark remover;
based on the code word mark removal signal, determining the second number of clock cycles during which the receiver data stream is to be halted; and
generating and transmitting a receiver data halt signal indicating the second number of clock cycles to the code word mark removal compensation logic and the other receiver components.

12 . The physical layer transceiver of claim 11 , the code word mark removal compensation logic and the other receiver components receiving the receiver data halt signal from the receiver data path controller and, in response to the receiver data halt signal, halting all functions for the second number of clock cycles indicated.

13 . The physical layer transceiver of claim 8 , the other transmitter components comprising:
an encoder and scrambler within the portion of the transmitter data path within the physical coding sub-layer, the encoder and scrambler receiving the transmitter data stream through a media independent interface and encoding and scrambling the transmitter data stream; and a transcoder within the portion of the transmitter data path within the forward error correction sub-layer, the transcoder receiving the transmitter data stream directly from the encoder and scrambler following the encoding and the scrambling, transcoding the transmitter data stream, and providing the transmitter data stream to the code word mark inserter following the transcoding.

14 . The physical layer transceiver of claim 11 , the other receiver components comprising:
a decoder and descrambler in the portion of the receiver data path within the physical coding sub-layer; and a transcoder in the portion of the receiver data

Assignees

• Globalfoundries Inc

Inventors

• Yang Kai
• Liu Yang
• Yin Jilei
• Jiang Wei

Classifications

• H04L1/004 Primary

  by using forward error control (H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00) · CPC title

• H04L1/0043

  Realisations of complexity reduction techniques, e.g. use of look-up tables · CPC title

• H04L1/0052 Primary

  Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables · CPC title

• H04L69/323

  in the physical layer [OSI layer 1] · CPC title

• H04L1/0041

  Arrangements at the transmitter end · CPC title