Ltps array substrate and manufactoring method thereof

Patent metadata

Field	Value
Publication number	US-2018122829-A1
Application number	US-201715853832-A
Country	US
Kind code	A1
Filing date	Dec 24, 2017
Priority date	Jul 24, 2015
Publication date	May 3, 2018
Grant date	—

Abstract

A method for manufacturing a LTPS array substrate includes: forming a source electrode and a drain electrode on a substrate, forming a poly-silicon layer in a first region and a second region of the substrate including the source electrode and the drain electrode, such that the poly-silicon layer of the first region has a thickness greater than that of the second region and the poly-silicon layer of the first region partially covers the source electrode and the drain electrode; passivating a surface of the poly-silicon layer in order to turn a part of the poly-silicon layer of the second region and the first region that is adjacent to the surface into an insulating layer; and forming a gate electrode on the insulating layer between the source electrode and the drain electrode. The LTPS technical process is simple and can reduce the producing costs.

First claim

What is claimed is:

1 . A low temperature poly-silicon (LTPS) array substrate, comprising:
a substrate; a source electrode and a drain electrode, which are arranged on the substrate; a poly-silicon layer, which is arranged on the substrate including the source electrode and the drain electrode, wherein the poly-silicon layer partially covers the source electrode and the drain electrode; an insulating layer, which is arranged on the poly-silicon layer and the source and drain electrodes, wherein the insulating layer is formed through passivation of a part of the poly-silicon layer that covers the substrate including the source electrode and the drain electrode; a gate electrode, which is arranged on the insulating layer between the source electrode and the drain electrode, wherein the source and drain electrodes, the poly-silicon layer, and the gate electrode collectively form a thin-film transistor (TFT); a planar layer, which is arranged on the substrate including the gate electrode, wherein the planar layer is formed with a contact hole extending therethrough to expose a surface of the drain electrode; a common electrode, which is arranged on the planar layer except the TFT of the LTPS array substrate; a passivation layer, which is arranged on the planar layer and the common electrode layer, such that the passivation layer does not cover the contact hole; a pixel electrode, which is arranged on the passivation layer, wherein the pixel electrode is electrically connected with the drain electrode through the contact hole.

2 . The LTPS array substrate as claimed in claim 1 , wherein the passivation of the poly-silicon layer comprises one of oxidation treatment, nitriding treatment, and a combination thereof.

Assignees

• Shenzhen China Star Optoelect
• Wuhan China Star Optoelectronics Technology Co Ltd
• Shenzhen China Star Optoelect
• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Wang Cong
• Du Peng
• Wang Xiaoxiao

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10P14/6316

  Formation by nitridation, e.g. nitridation of the substrate · CPC title

• H10P14/6318

  Formation by simultaneous oxidation and nitridation · CPC title

• H10P14/6304

  Formation by oxidation, e.g. oxidation of the substrate · CPC title

• H10P14/6903

  containing silicon · CPC title