Semiconductor device and manufacturing method thereof

US2018102431A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2018102431-A1
Application numberUS-201715837520-A
CountryUS
Kind codeA1
Filing dateDec 11, 2017
Priority dateJul 23, 2015
Publication dateApr 12, 2018
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device including an isolation insulating film having a first thickness that is located between a drain region and a source region; a gate electrode formed over a region located between the isolation insulating film and the source region and that includes a part serving as a channel; an interlayer insulating film formed so as to cover the gate electrode; and a contact plug formed to reach the inside of the isolation insulating film while penetrating the interlayer insulating film, wherein the contact plug includes a buried part that is formed from the surface of the isolation insulating film up to a depth corresponding to a second thickness thinner than the first thickness.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor device including: a semiconductor substrate having a primary surface; a first-conductive-type first semiconductor layer that is formed over the primary surface of the semiconductor substrate; a second-conductive-type drain region that is formed in the first semiconductor layer; a second-conductive-type source region that is formed in the first semiconductor layer at a distance away from the drain region; an isolation insulating film having a first thickness that is formed at a part of the first semiconductor layer located between the drain region and the source region; a second-conductive-type drift layer that is formed from the surface of the first semiconductor layer up to a position deeper than the bottom of the isolation insulating film so as to surround the isolation insulating film and the drain region from the lateral and lower sides; a gate electrode that is formed over a region located between the isolation insulating film and the source region and including a part serving as a channel; an interlayer insulating film that is formed so as to cover the gate electrode; and a contact plug that is formed to reach the inside of the isolation insulating film while penetrating the interlayer insulating film, wherein the contact plug includes a buried part that is formed from the surface of the isolation insulating film up to a depth corresponding to a second thickness thinner than the first thickness. 2 . The semiconductor device according to claim 1 , wherein the contact plug and the drain region are electrically coupled to each other, and wherein a voltage same as that applied to the drain region is applied to the contact plug. 3 . The semiconductor device according to claim 1 , wherein the contact plug is arranged in the isolation insulating film on the side where the part serving as the channel is located, and wherein a voltage different from that applied to the drain region is applied to the contact plug. 4 . The semiconductor device according to claim 3 , wherein provided is a voltage applying part that includes, at least, any one of a resistive element and a capacitive element and applies to the contact plug a voltage between a drain voltage applied to the drain region and a source voltage applied to the source region. 5 . The semiconductor device according to claim 3 , wherein provided is a voltage applying part that includes, at least, any one of a resistive element and a capacitive element and applies to the contact plug a voltage between a gate voltage applied to the gate electrode and a voltage applied to the source region. 6 . The semiconductor device according to claim 1 , wherein the drain region is formed so as to extend in a first direction over the surface of the first semiconductor layer, wherein the isolation insulating film is formed so as to continuously surround the drain region over the surface of the first semiconductor layer; and wherein the source region is formed so as to continuously surround the isolation insulating film over the surface of the first semiconductor layer. 7 . The semiconductor device according to claim 6 , wherein the buried part of the contact plug is formed so as to continuously surround the drain region in the isolation insulating film. 8 . The semiconductor device according to claim 6 , wherein the buried part of the contact plug is continuously formed along the first direction. 9 . The semiconductor device according to claim 6 , wherein a plurality of buried parts of contact plugs is formed in the first direction at a distance away from each other. 10 . The semiconductor device according to claim 6 , wherein a plurality of contact plugs is arranged in the first direction at a distance away from each other, and wherein the gate electrode includes a part extending between the contact plugs that are adjacent to each other. 11 . The semiconductor device according to claim 6 , wherein the contact plug includes a first contact part that applies a first voltage to the contact plug and is arranged at apart of the contact plug located on the one end side of the drain region in the longitudinal direction, and wherein a second contact part applies a second voltage to the gate electrode and is arranged at a part of the gate electrode located on the other end side of the drain region in the longitudinal direction. 12 . The semiconductor device according to claim 1 , wherein another gate electrode is formed over apart of the isolation insulating film located between the drain region and the contact plug and is electrically coupled to the gate electrode. 13 . The semiconductor device according to claim 1 , wherein the contact plug includes: a buried electrode first part; and a buried electrode second part that is arranged on the side where the gate electrode is located relative to the buried electrode first part, wherein a voltage same as the drain voltage applied to the drain region is applied to the buried electrode first part, and wherein a voltage different from the drain voltage is applied to the buried electrode second part. 14 . The semiconductor device according to claim 1 , wherein the buried part of the contact plug includes a part located immediately under the gate electrode. 15 . The semiconductor device according to claim 1 , wherein a second-conductive-type buried layer is formed between the semiconductor substrate and the first semiconductor layer. 16 . The semiconductor device according to claim 1 , wherein a first-conductive-type RESURF layer is formed in the first semiconductor layer. 17 . The semiconductor device according to claim 1 , wherein a buried oxide film is formed between the semiconductor substrate and the first semiconductor layer. 18 . The semiconductor device according to claim 1 , wherein the isolation insulating film is formed in a trench provided in the first semiconductor layer. 19 . A manufacturing method of a semiconductor device including: forming a first-conductive-type first semiconductor layer over the primary surface of a semiconductor substrate; forming an isolation insulating film having a first thickness over the first semiconductor layer; forming a second-conductive-type drift layer from the surface of the first semiconductor layer up to a position deeper than the bottom of the isolation insulating film so as to surround the isolation insulating film from the lateral and lower sides; forming a gate electrode over the first semiconductor layer so as to extend from the isolation insulating film; forming a second-conductive-type drain region at apart of the drift layer located on the side opposite to the buried electrode in the isolation insulating film and forming a second-conductive-type source region at a part of the first semiconductor layer located on the side opposite to the isolation insulating film in the gate electrode; forming an interlayer insulating film so as to cover the gate electrode, the isolation insulating film, the drain region, and the source region; forming a contact hole including an opening having a depth corresponding to a second thickness thinner than the first thickness from the surface of the isolation insulating film while penetrating the interlayer insulating film by etching the interlayer insulating film and the isolation insulating film; and forming a contact plug in the contact hole, wherein the step of forming a contact plug includes a step of forming a buried part in t

Assignees

Inventors

Classifications

  • of insulating materials · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

  • of the semiconductor materials · CPC title

  • having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

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What does patent US2018102431A1 cover?
A semiconductor device including an isolation insulating film having a first thickness that is located between a drain region and a source region; a gate electrode formed over a region located between the isolation insulating film and the source region and that includes a part serving as a channel; an interlayer insulating film formed so as to cover the gate electrode; and a contact plug formed…
Who is the assignee on this patent?
Renesas Electronics Corp
What technology area does this patent fall under?
Primary CPC classification H01L29/7823. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Apr 12 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).