Linear masking circuits for side-channel immunization of advanced encryption standard hardware

Patent metadata

Field	Value
Publication number	US-2018097618-A1
Application number	US-201615283000-A
Country	US
Kind code	A1
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Apr 5, 2018
Grant date	—

Abstract

Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.

First claim

1 . An apparatus comprising:
a first circuitry operable to convert a value on an input of the first circuitry into a value on an output of the first circuitry in accordance with an encryption matrix; a second circuitry operable to provide a sequence of pseudo-random numbers on a first output of the second circuitry and a registered copy of the sequence on a second output of the second circuitry; and a third circuitry operable to provide an XOR of a value on the output of the first circuitry and a value on the first output of the second circuitry onto an output of the third circuitry coupled to an input of a fourth circuitry.

2 . The apparatus of claim 1 , comprising:
a fifth circuitry operable to provide an XOR of a value on an output of the fourth circuitry, a value coupled to an output of a sixth circuitry, and a value on the second output of the second circuitry onto an output of the fifth circuitry coupled to the input of the first circuitry.

3 . The apparatus of claim 1 ,
wherein the second circuitry comprises a Linear-Feedback Shift Register (LFSR).

4 . The apparatus of claim 1 ,
wherein a width of at least one of the following is an integer number of bytes: the input of the first circuitry, the output of the first circuitry, the first output of the second circuitry, the second output of the second circuitry, the output of the third circuitry, the input of the fourth circuitry, the output of the fourth circuitry, the output of the sixth circuitry, and the output of the fifth circuitry.

5 . The apparatus of claim 1 ,
wherein a width of at least one of the following is two bytes: the input of the first circuitry, the output of the first circuitry, the first output of the second circuitry, the second output of the second circuitry, the output of the third circuitry, the input of the fourth circuitry, the output of the fourth circuitry, the output of the sixth circuitry, and the output of the fifth circuitry.

6 . The apparatus of claim 1 , comprising:
a seventh circuitry operable to convert a value on an input of the seventh circuitry into a value on an output of the seventh circuitry in accordance with a transformation process.

7 . The apparatus of claim 6 , comprising:
an eighth circuitry having at least a first input coupled to the output of the fourth circuitry, a second input coupled to the output of the seventh circuitry, a selection input, and an output coupled to the input of the fourth circuitry.

8 . The apparatus of claim 6 comprising:
a ninth circuitry having at least a first input coupled to the output of the first circuitry, a second input coupled to the output of the third circuitry, a selection input, and an output coupled to the input of the seventh circuitry.

9 . The apparatus of claim 1 comprising:
a tenth circuitry having at least a first input coupled to the output of the sixth circuitry, a second input coupled to an XOR of the output of the sixth circuitry and the output of the fourth circuitry, a selection input, and an output coupled to the input of the first circuitry.

10 . The apparatus of claim 8 , comprising:
an eleventh circuitry having at least a first input coupled to the output of the tenth circuitry, a second input coupled to the output of the fifth circuitry, a selection input, and an output coupled to the input of the first circuitry.

11 . The apparatus of claim 8 , comprising:
a twelfth circuitry operable to provide an inversion of a value on an input of the twelfth circuitry to an output of the twelfth circuitry, the input of the twelfth circuitry being coupled to the output of the tenth circuitry; a thirteenth circuitry operable to provide an inversion of a value on an input of the thirteenth circuitry to an output of the thirteenth circuitry, the input of the thirteenth circuitry being coupled to the output of the fourth circuitry; and a fourteenth circuitry operable to perform an XOR of a value on the output of the twelfth circuitry and a value on the output of the thirteenth circuitry.

12 . A system comprising a memory, a processor coupled to the memory, and a wireless interface for allowing the processor to communicate with another device, the system including the apparatus of claim 1 .

13 . A system comprising a memory, a processor coupled to the memory, and a wireless interface for allowing the processor to communicate with another device, the processor including:
a first circuitry operable to convert a value on an input of the first circuitry into a value on an output of the first circuitry in accordance with an encryption matrix; a second circuitry operable to provide a sequence of pseudo-random numbers on a first output of the second circuitry and a registered copy of the sequence on a second output of the second circuitry; and a third circuitry operable to provide an XOR of a value on the output of the first circuitry and a value on the first output of the second circuitry onto an output of the third circuitry coupled to an input of a fourth circuitry.

14 . The system of claim 13 , comprising:
a fifth circuitry operable to provide an XOR of a value on an output of the fourth circuitry, a value coupled to an output of a sixth circuitry, and a value on the second output of the second circuitry onto an output of the fifth circuitry coupled to the input of the first circuitry; a seventh circuitry operable to convert a value on an input of the seventh circuitry into a value on an output of the seventh circuitry in accordance with a transformation process, wherein the second circuitry comprises a Linear-Feedback Shift Register (LFSR).

15 . The system of claim 14 , comprising:
an eighth circuitry having at least a first input coupled to the output of the fourth circuitry, a second input coupled to the output of the seventh circuitry, a selection input, and an output coupled to the input of the fourth circuitry; a ninth circuitry having at least a first input coupled to the output of the first circuitry, a second input coupled to the output of the third circuitry, a selection input, and an output coupled to the input of the seventh circuitry; a tenth circuitry having at least a first input coupled to the output of the sixth circuitry, a second input coupled to an XOR of the output of the sixth circuitry and the output of the fourth circuitry, a selection input, and an output coupled to the input of the first circuitry; and an eleventh circuitry having at least a first input coupled to the output of the tenth circuitry, a second input coupled to the output of the fifth circuitry, a selection input, and an output coupled to the input of the first circuitry.

16 . The system of claim 15 , comprising:
a twelfth circuitry operable to provide an inversion of a value on an input of the twelfth circuitry to an output of the twelfth circuitry, the input of the twelfth circuitry being coupled to the output of the tenth circuitry; a thirteenth circuitry operable to provide an inversion of a value on an input of the thirteenth circuitry to an output of the thirteenth circuitry, the input of the thirteenth circuitry being coupled to the output of the fourth circuitry; and a fourteenth circuitry operable to perform an XOR of a value on the output of the twelfth circuitry and a value on the output of the thirteenth circuitry.

17 . An apparatus comprising:
a first circuitry operable to convert a value on an input of the first circuitry into a value on an output of the first circuitry in accordance with an encryption matrix; a second circuitry operable to provide an inversion of a value on an

Assignees

• Intel Corp

Inventors

• Kumar Raghavan
• Mathew Sanu K
• Varna Avinash L
• Suresh Vikram B
• Satpathy Sudhir K

Classifications

• H04L2209/046

  of operations, operands or results of the operations · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• G09C1/00 Primary

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L9/003

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title

• H04L9/0631

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title