High efficiency linearization power amplifier for wireless communication

Patent metadata

Field	Value
Publication number	US-2018097530-A1
Application number	US-201715682431-A
Country	US
Kind code	A1
Filing date	Aug 21, 2017
Priority date	May 1, 2002
Publication date	Apr 5, 2018
Grant date	—

Abstract

A method and a predistortion system for linearizing an output of a power amplifier include receiving a first input signal representative of an analog RF modulated signal of the predistortion system, receiving a digitized reference signal representative of an idealized reference signal, and receiving a digitized feedback signal representative of nonlinear characteristics of the power amplifier. The method further includes generating, using a lookup table, a predistortion correction signal based on an error between the digitized reference signal and the digitized feedback signal. The first input signal and the predistortion correction signal are combined to produce a predistortion signal that is supplied to the power amplifier to linearize the output of the power amplifier.

First claim

1 . (canceled)

2 . A predistortion system for linearizing an output of a power amplifier, the predistortion system comprising:
a first input operable to receive a first input signal representative of an analog RF modulated signal; a second input operable to receive a digitized reference signal representative of an idealized reference signal; a third input operable to receive a digitized feedback signal representative of nonlinear characteristics of the power amplifier; a predistortion controller operable to generate, using a lookup table, a predistortion correction signal based on an error between the digitized reference signal and the digitized feedback signal; and combining logic operable to combine the first input signal and the predistortion correction signal to produce a predistortion signal that is supplied to the power amplifier to linearize the output of the power amplifier.

3 . The predistortion system of claim 2 , further comprising:
error logic operable to determine the error as a difference between a square of the digitized reference signal and a square of the digitized feedback signal.

4 . The predistortion system of claim 2 , further comprising:
a multiplier operable to multiply the error by an adaptive factor.

5 . The predistortion system of claim 2 , wherein the lookup table receives, as a first input, an address derived from the digitized reference signal.

6 . The predistortion system of claim 5 , wherein the predistortion controller further comprises an address former operable to generate the address based on the digitized reference signal.

7 . The predistortion system of claim 5 , wherein the lookup table receives, as a second input, an error signal derived from the error and from a previous value output by the lookup table.

8 . The predistortion system of claim 2 , wherein the digitized reference signal and the digitized feedback signal each include an in-phase component and a quadrature component, and wherein the predistortion controller is operable to form a first component of the predistortion correction signal using the in-phase components and a second component of the predistortion correction signal using the quadrature components.

9 . The predistortion system of claim 8 , wherein the predistortion controller is operable to perform a first lookup in the lookup table for the in-phase component of the digitized reference signal and a second lookup in the lookup table for the quadrature component of the digitized reference signal.

10 . A method for linearizing an output of a power amplifier, the method comprising:
receiving a first input signal representative of an analog RF modulated signal of a predistortion system; receiving a digitized reference signal representative of an idealized reference signal; receiving a digitized feedback signal representative of nonlinear characteristics of the power amplifier; generating, using a lookup table, a predistortion correction signal based on an error between the digitized reference signal and the digitized feedback signal; and combining the first input signal and the predistortion correction signal to produce a predistortion signal that is supplied to the power amplifier to linearize the output of the power amplifier.

11 . The method of claim 10 , further comprising:
determining the error as a difference between a square of the digitized reference signal and a square of the digitized feedback signal.

12 . The method of claim 10 , further comprising:
multiplying the error by an adaptive factor.

13 . The method of claim 10 , further comprising:
receiving, as a first input to the lookup table, an address derived from the digitized reference signal.

14 . The method of claim 13 , further comprising:
receiving, as a second input to the lookup table, an error signal derived from the error and from a previous value output by the lookup table.

15 . The method of claim 10 , wherein the digitized reference signal and the digitized feedback signal each include an in-phase component and a quadrature component, the method further comprising:
forming a first component of the predistortion correction signal using the in-phase components and; forming a second component of the predistortion correction signal using the quadrature components.

16 . The predistortion system of claim 15 , further comprising:
performing a first lookup in the lookup table for the in-phase component of the digitized reference signal; and performing a second lookup in the lookup table for the quadrature component of the digitized reference signal.

Assignees

• Dali Wireless Inc

Inventors

• Yang Dali
• Yang Jia

Classifications

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2201/3233

  Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion · CPC title

• H03F3/24

  of transmitter output stages · CPC title

• H03F2201/3215

  To increase the output power or efficiency · CPC title

• H03F3/21

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title