Semiconductor device and method of forming duplex plated bump-on-lead pad over substrate for finer pitch between adjacent traces
US-9799621-B2 · Oct 24, 2017 · US
Interconnection substrate and semiconductor package
US2018096926A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018096926-A1 |
| Application number | US-201715718414-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 28, 2017 |
| Priority date | Oct 5, 2016 |
| Publication date | Apr 5, 2018 |
| Grant date | — |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
An interconnection substrate includes a first insulating layer, and an interconnection structure formed on the first insulating layer, wherein the interconnection structure includes an interconnection pattern having a first metal layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer, and a fourth metal layer covering an upper surface and side surface of the interconnection pattern, wherein an outer perimeter of the second metal layer protrudes at the side surface of the interconnection pattern to form a first protrusion, and the fourth metal layer has a second protrusion that protrudes at a side surface of the interconnection structure at a position corresponding to the first protrusion.
First claim
Opening claim text (preview).
What is claimed is: 1 . An interconnection substrate, comprising: a first insulating layer; and an interconnection structure formed on the first insulating layer, wherein the interconnection structure includes: an interconnection pattern having a first metal layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer; and a fourth metal layer covering an upper surface and side surface of the interconnection pattern, wherein an outer perimeter of the second metal layer protrudes at the side surface of the interconnection pattern to form a first protrusion, and the fourth metal layer has a second protrusion that protrudes at a side surface of the interconnection structure at a position corresponding to the first protrusion. 2 . The interconnection substrate as claimed in claim 1 , wherein the fourth metal layer is made of an alloy containing nickel as a main component, and the first metal layer and the third metal layer are made of a metal whose standard electrode potential is positive relative to nickel and that is inactive against a reducing agent for electroless nickel plating, and wherein the second metal layer is made of a metal that exhibits a catalytic activity toward the reducing agent for electroless nickel plating. 3 . The interconnection substrate as claimed in claim 2 , wherein the first metal layer and the third metal layer are made of copper, and the second metal layer is made of palladium or nickel. 4 . The interconnection substrate as claimed in claim 1 , further comprising a fifth metal layer between an upper surface of the first insulating layer and a lower surface of the first metal layer, a side surface of the fifth metal layer being covered with the fourth metal layer. 5 . The interconnection substrate as claimed in claim 1 , further comprising a second insulating layer formed on the first insulating layer to cover the interconnection structure. 6 . A semiconductor package, comprising: the interconnection substrate of claim 1 ; a semiconductor chip mounted on the interconnection substrate and electrically coupled to the interconnection structure; and insulating resin filling a gap between the interconnection substrate and the semiconductor chip and covering the interconnection structure.
Assignees
Inventors
Classifications
used as a support during the manufacture of self-supporting substrates · CPC title
Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title
using temporarily an auxiliary support · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
the encapsulations exposing the passive side of the semiconductor body · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2018096926A1 cover?
- An interconnection substrate includes a first insulating layer, and an interconnection structure formed on the first insulating layer, wherein the interconnection structure includes an interconnection pattern having a first metal layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer, and a fourth metal layer covering an upper surfa…
- Who is the assignee on this patent?
- Shinko Electric Ind Co
- What technology area does this patent fall under?
- Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Apr 05 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).