Chamber with flow-through source

US2018096818A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2018096818-A1
Application numberUS-201615285176-A
CountryUS
Kind codeA1
Filing dateOct 4, 2016
Priority dateOct 4, 2016
Publication dateApr 5, 2018
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Described processing chambers may include a chamber housing at least partially defining an interior region of a semiconductor processing chamber. The chamber may include a showerhead positioned within the chamber housing, and the showerhead may at least partially divide the interior region into a remote region and a processing region in which a substrate can be contained. The chamber may also include an inductively coupled plasma source positioned between the showerhead and the processing region. The inductively coupled plasma source may include a conductive material within a dielectric material.

First claim

Opening claim text (preview).

1 . A semiconductor processing chamber comprising: a chamber housing at least partially defining an interior region of the semiconductor processing chamber; a showerhead positioned within the chamber housing, wherein the showerhead at least partially divides the interior region into a remote region and a processing region in which a substrate can be contained; and an inductively coupled plasma source positioned between the showerhead and the processing region, wherein the inductively coupled plasma source comprises a conductive material within a dielectric material. 2 . The semiconductor processing chamber of claim 1 , wherein the dielectric material is selected from the group consisting of aluminum oxide, yttrium oxide, single crystalline silicon, and quartz. 3 . The semiconductor processing chamber of claim 1 , wherein the conductive material comprises a copper tube configured to receive a fluid flowed within the tube. 4 . The semiconductor processing chamber of claim 1 , wherein the dielectric material defines apertures through the inductively coupled plasma source, and wherein the conductive material is positioned about the apertures within the dielectric material. 5 . The semiconductor processing chamber of claim 1 , wherein the apertures are included in a uniform pattern across the dielectric material and about the conductive material. 6 . The semiconductor processing chamber of claim 1 , wherein the conductive material is configured in a planar spiral pattern within the dielectric material. 7 . The semiconductor processing chamber of claim 1 , wherein the conductive material is configured in a coil extending vertically within the dielectric material for at least two complete turns of the conductive material. 8 . The semiconductor processing chamber of claim 1 , wherein the conductive material comprises two conductive tubes positioned within the inductively coupled source. 9 . The semiconductor processing chamber of claim 8 , wherein a first tube is included in a first configuration within the inductively coupled source, wherein a second tube is included in a second configuration within the inductively coupled source, and wherein the second configuration is radially inward of the first configuration. 10 . The semiconductor processing chamber of claim 9 , wherein the first configuration and the second configuration are each coiled configurations extending vertically within the dielectric material. 11 . The semiconductor processing chamber of claim 9 , wherein the first configuration and the second configuration are each a planar configuration within the same plane of the inductively coupled source. 12 . The semiconductor processing chamber of claim 9 , wherein the first tube and the second tube are coupled with an RF source. 13 . The semiconductor processing chamber of claim 12 , wherein the first tube and the second tube are each coupled with the RF source through a capacitive divider. 14 . The semiconductor processing chamber of claim 1 , wherein the inductively coupled source comprises at least two plates coupled together, wherein each plate defines at least a portion of a channel, and wherein the conductive material is housed within the channel at least partially defined by each of the at least two plates. 15 . An inductively coupled plasma source comprising: a first plate defining at least a portion of a first channel and at least a portion of a second channel within the first plate, wherein the first plate comprises a dielectric material; a first conductive material seated within the at least a portion of the first channel; and a second conductive material seated within the at least a portion of the second channel, wherein each of the first conductive material and the second conductive material is characterized by a spiral or coil configuration, and wherein each of the first conductive material and the second conductive material is coupled with an RF source. 16 . The inductively coupled plasma source of claim 15 , wherein the first plate defines apertures through the first plate, and wherein a central axis of each aperture is normal to the at least a portion of the channel. 17 . The inductively coupled plasma source of claim 15 , wherein the source comprises a thickness of at least three inches. 18 . (canceled) 19 . The inductively coupled plasma source of claim 15 , further comprising a second plate coupled with the first plate enclosing the conductive material between the first plate and the second plate, wherein the second plate defines second apertures axially aligned with the apertures defined through the first plate. 20 . A semiconductor processing chamber comprising: a chamber housing at least partially defining an interior region of the semiconductor processing chamber, wherein the chamber housing includes a lid assembly including an inlet for receiving precursors into the semiconductor processing chamber; a pedestal within the interior region of the semiconductor processing chamber; a showerhead positioned within the chamber housing, wherein the showerhead is positioned between the lid assembly and the pedestal; an inductively coupled plasma source positioned between the showerhead and the pedestal, wherein the inductively coupled plasma source comprises a conductive material within a dielectric material.

Assignees

Inventors

Classifications

  • of Group IV materials · CPC title

  • Apparatus for manufacture or treatment · CPC title

  • having particular electrical resistive or conductive properties · CPC title

  • for applying thin layers on objects · CPC title

  • Windows · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2018096818A1 cover?
Described processing chambers may include a chamber housing at least partially defining an interior region of a semiconductor processing chamber. The chamber may include a showerhead positioned within the chamber housing, and the showerhead may at least partially divide the interior region into a remote region and a processing region in which a substrate can be contained. The chamber may also i…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H01J37/3053. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Apr 05 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).