Method and device for a finfet
US-2016204105-A1 · Jul 14, 2016 · US
Semiconductor device blocking leakage current and method of forming the same
US2018090589A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018090589-A1 |
| Application number | US-201715820171-A |
| Country | US |
| Kind code | A1 |
| Filing date | Nov 21, 2017 |
| Priority date | Jun 8, 2015 |
| Publication date | Mar 29, 2018 |
| Grant date | — |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device, comprising: a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly; a contact assembly disposed on the gate spacer; an air gap disposed between the device isolation layer and the contact assembly; and a first spacer capping layer disposed between the gate spacer and the air gap, wherein the first spacer capping layer has an etch selectivity with respect to the gate spacer.
Assignees
Inventors
Classifications
by forming self-aligned vias or self-aligned contact plugs · CPC title
of dielectric parts comprising air gaps · CPC title
comprising air gaps · CPC title
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title
formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2018090589A1 cover?
- A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has a…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H01L29/4991. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Mar 29 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).