Semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-2018090214-A1
Application number	US-201715703368-A
Country	US
Kind code	A1
Filing date	Sep 13, 2017
Priority date	Sep 28, 2016
Publication date	Mar 29, 2018
Grant date	—

Abstract

A semiconductor integrated circuit includes a first circuit, a second circuit, a memory circuit having a plurality of flip-flops, a storage unit, a signal generating unit to produce an operation mode setting signal, a control circuit configured to cause the memory circuit to operate such that the plurality of flip-flops holds a value for setting characteristics of the first circuit when the operation mode setting signal indicates a first operation mode, and configured to cause the memory circuit to operate as a counter to measure a time length used in the second circuit when the operation mode setting signal indicates a second operation mode, and a setting circuit configured to cause trimming data stored in the storage unit to set the characteristic of the first circuit when the operation mode setting signal indicates the second operation mode, the trimming data corresponding to the value held by the memory circuit.

First claim

What is claimed is

1 . A semiconductor integrated circuit, comprising:
a first circuit; a second circuit; a memory circuit having a plurality of flip-flops; a storage unit implemented as nonvolatile memory elements; a signal generating unit implemented as one or more nonvolatile memory elements to produce an operation mode setting signal for selecting one of a plurality of operation modes; a control circuit configured to cause the memory circuit to operate such that the plurality of flip-flops holds a value for setting characteristics of the first circuit when the signal generating circuit produces the operation mode setting signal indicative of a first operation mode, and configured to cause the memory circuit to operate as a counter to measure a time length used in the second circuit when the signal generating circuit produces the operation mode setting signal indicative of a second operation mode; and a setting circuit configured to cause trimming data stored in the storage unit to set the characteristic of the first circuit to correct product variation therein when the signal generating circuit produces the operation mode setting signal indicative of the second operation mode, the trimming data corresponding to the value held by the memory circuit.

2 . The semiconductor integrated circuit as claimed in claim 1 , wherein the time length used in the second circuit relates to a delay time of a protective operation for a secondary battery.

3 . The semiconductor integrated circuit as claimed in claim 1 , wherein the storage unit is a memory that is one-time programmable through blowing of fuses.

4 . The semiconductor integrated circuit as claimed in claim 1 , wherein the control circuit is configured to cause the value held by the memory circuit to be set to the plurality of flip-flops one bit at a time through consecutive comparisons.

Assignees

• Yamaguchi Takeshi
• Mitsumi Electric Co Ltd

Inventors

• Yamaguchi Takeshi

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/28 Primary

  using differential sensing or reference cells, e.g. dummy cells · CPC title