Offload data transfer engine for a block data transfer interface

Patent metadata

Field	Value
Publication number	US-2018089099-A1
Application number	US-201615280965-A
Country	US
Kind code	A1
Filing date	Sep 29, 2016
Priority date	Sep 29, 2016
Publication date	Mar 29, 2018
Grant date	—

Abstract

In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

First claim

What is claimed is:

1 . A system, comprising:
at least one central processing unit; a memory having a destination memory which includes a first destination region configured to store a first block of data, and a second destination region configured to store a second block of data, wherein the memory further has a data structure memory configured to store an address map data structure to map a first logical address to a first physical address of the first destination region, a source memory configured to store a block of update data to update data of the first block of data, and a command set memory configured to store a data transfer command set from a central processing unit, the data transfer command set including at least one data transfer command from a central processing unit to transfer a block of data, from the source memory to the destination memory; a data path coupling the source memory to the destination memory wherein the data path bypasses the central processing unit; an offload data transfer engine configured to execute the data transfer command set, wherein the offload data transfer engine includes:
data transfer logic, configured to be responsive to at least one command of the data transfer command set, to transfer the block of update data in the data path from the source memory to the second region of the destination memory, wherein the data path bypasses the central processing unit; and
transfer status logic, configured to be responsive to at least one command of the data transfer command set to confirm successful transfer of the block of update data, and to provide a successful transfer indication of successful transfer of the block of update data to the second region; and
address map update logic, configured to be responsive to the successful transfer indication, to re-map the first logical address to a second physical address of the second region of the destination memory, instead of the first physical address of the first region of the destination memory.

2 . The system of claim 1 wherein the data structure memory is further configured to store a free region log data structure having entries to indicate free regions of the destination memory, the system further comprising log update logic configured to update an entry of a free region log data structure to indicate that the first region is available for use to store other data, after the first logical address is re-mapped to the second region of the destination memory.

3 . The system of claim 1 wherein the address map data structure includes a block transfer table comprising entries wherein each block transfer table entry is configured to map a logical address to a physical address of the destination memory and wherein the address map update logic is further configured to be responsive to the successful transfer indication, to update a block transfer table entry to re-map the first logical address to a second physical address of the second region of the destination memory, instead of the first physical address of the first region of the destination memory.

4 . The system of claim 3 wherein the address map update logic is further configured to acquire a block aperture region resource, program the block aperture region resource to point to an entry of the block transfer table, and perform an atomic write to the entry so that the first logical address is mapped to the second physical address of the second region of the destination memory, to update a block transfer table entry.

5 . The system of claim 1 wherein the offload data transfer engine includes the address map update logic and wherein the data transfer command set includes at least one map data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of map entry data by the offload data transfer engine, from a source memory to a data structure memory, wherein the address map update logic is configured to be responsive to the map data transfer command, to transfer the map entry data from a source memory to a data structure memory so that the first logical address is mapped to the second physical address of the second region of the destination memory.

6 . The system of claim 2 wherein the offload data transfer engine includes the log update logic and wherein the data transfer command set includes at least one log data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of free region log data structure entry data by the offload data transfer engine, from a source memory to a data structure memory wherein the log update logic is configured to be responsive to the log data transfer command, to transfer the free region log data structure entry data from a source memory to a data structure memory so that the updating causes the free region log to indicate that the first region is available for use to store other data.

7 . The system of claim 1 , wherein the offload data transfer engine further includes error handling logic configured to, in response to the data transfer command set:
detect an error in transferring data from the source memory to the destination memory; and in response to error detection, stop the transfer of data from the source memory to the destination memory, provide a transfer failure indication of unsuccessful transfer of data to the destination memory, and leave the mapping of the first logical address to the first physical address of the first region of the destination memory unchanged.

8 . The system of claim 2 wherein the offload data transfer engine includes the address map update logic and wherein the data transfer command set includes at least one map data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of map entry data by the offload data transfer engine, from a source memory to a data structure memory, wherein the address map update logic is configured to be responsive to the map data transfer command and responsive to the successful transfer indication, to transfer the map entry data from a source memory to a data structure memory so that the first logical address is mapped to the second physical address of the second region of the destination memory;
wherein the offload data transfer engine further includes the log update logic and wherein the data transfer command set includes at least one log data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of free region log data structure entry data by the offload data transfer engine, from a source memory to a data structure memory wherein the log update logic is configured to be responsive to the log data transfer command, to transfer the free region log data structure entry data from a source memory to a data structure memory so that the updating causes the free region log to indicate that the first region is available for use to store other data and
wherein the offload data transfer engine further includes error handling logic configured to, in response to the data transfer command set:
detect an error in transferring data from the source memory to a memory; and
in response to error detection, stop the transfer of data, provide a transfer failure indication of unsuccessful transfer of data, leave the mapping of the first logical address to the first physical address of the first region of the destination memory unchanged, and leave the free region log unchanged to indicate that the first region is unavailable for use to store other data.

9 . A method, comprising:
forwarding a data transfer command set including at least one data transfer command from a central processing unit to an offload data

Assignees

• Intel Corp

Inventors

• Raj Ashok
• Radhakrishnan Sivakumar
• Williams Dan J
• Verma Vishal
• Ranganathan Narayan
• Douglas Chet R

Classifications

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title