Clock synchronization

Patent metadata

Field	Value
Publication number	US-2018083763-A1
Application number	US-201615273015-A
Country	US
Kind code	A1
Filing date	Sep 22, 2016
Priority date	Sep 22, 2016
Publication date	Mar 22, 2018
Grant date	—

Abstract

An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.

First claim

What is claimed is:

1 . An apparatus comprising:
a first circuit configured to generate a clock inhibit signal; and a second circuit configured to generate a divided clock signal based, at least in part, on a clock select signal and the clock inhibit signal.

2 . The apparatus of claim 1 , wherein the second circuit is configured to generate the divided clock signal based on selecting a clock divider reference signal from at least one of a first clock signal or a second clock signal using the clock select signal.

3 . The apparatus of claim 2 , wherein the second circuit is configured to change the clock divider reference signal selection when the clock inhibit signal is asserted and maintain the clock divider reference signal selection when the clock inhibit signal is not asserted.

4 . The apparatus of claim 2 , further comprising:
a phase detector configured to determine a phase difference between a first reference signal and a second reference signal.

5 . The apparatus of claim 4 , wherein the second circuit is configured to change the clock divider reference signal selection based, at least in part, on the phase difference.

6 . The apparatus of claim 4 , wherein the divided clock signal has at least one of an approximately 90 degree phase difference or an approximately 180 degree phase difference with respect to the first reference signal.

7 . The apparatus of claim 6 , wherein the second reference signal is based, at least in part, on the divided clock signal.

8 . The apparatus of claim 4 , wherein the first reference signal and the second reference signal are based, at least in part, on a local oscillator clock signal.

9 . The apparatus of claim 2 , wherein the first clock signal and the second clock signal are gated clock signals having at least one clock cycle inhibited.

10 . A method for synchronizing a first clock signal and a second clock signal, the method comprising:
generating a clock inhibit signal; and generating a divided clock signal based, at least in part, on a clock select signal and the clock inhibit signal.

11 . The method of claim 10 , further comprising:
selecting, via the clock select signal, a clock divider reference signal from at least one of a first clock signal or a second clock signal.

12 . The method of claim 11 , further comprising:
changing the clock divider reference signal selection when the clock inhibit signal is asserted; and maintaining the clock divider reference signal selection when the clock inhibit signal is not asserted.

13 . The method of claim 11 , further comprising:
determining a phase difference between a first reference signal and a second reference signal.

14 . The method of claim 13 , further comprising:
changing the clock divider reference signal selection based, at least in part, on the phase difference.

15 . The method of claim 13 , wherein the divided clock signal has at least one of an approximately 90 degree phase difference or an approximately 180 degree phase difference with respect to the first reference signal.

16 . The method of claim 15 , wherein the second reference signal is based, at least in part, on the divided clock signal.

17 . The method of claim 13 , wherein the first reference signal and the second reference signal are based, at least in part, on a local oscillator clock signal.

18 . The method of claim 11 , wherein the first clock signal and the second clock signal are gated clock signals having at least one clock cycle inhibited.

19 . An apparatus comprising:
means for generating a clock inhibit signal; and means for generating a divided clock signal based, at least in part, on a clock select signal and the clock inhibit signal.

20 . The apparatus of claim 19 , wherein the clock select signal is utilized to select a clock divider reference signal from at least one of a first clock signal or a second clock signal to generate the divided clock signal.

21 . The apparatus of claim 20 , wherein the means for generating the divided clock signal comprises means for
changing the clock divider reference signal selection when the clock inhibit signal is asserted; and maintaining the clock divider reference signal selection when the clock inhibit signal is not asserted.

22 . The apparatus of claim 20 , further comprising:
means for determining a phase difference between a first reference signal and a second reference signal.

23 . The apparatus of claim 22 , wherein the means for generating the divided clock signal comprises means for changing the clock divider reference signal selection based, at least in part, on the phase difference.

24 . The apparatus of claim 22 , wherein the divided clock signal has at least one of an approximately 90 degree phase difference or an approximately 180 degree phase difference with respect to the first reference signal.

25 . The apparatus of claim 24 , wherein the second reference signal is based, at least in part, on the divided clock signal.

Assignees

• Qualcomm Inc

Inventors

• Black Justin
• Wang Cheng-Han
• Yang Jeongsik

Classifications

• H03J2200/11

  Cellular receiver, e.g. GSM, combined with a GPS receiver · CPC title

• H04W88/02

  Terminal devices · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H04W52/02

  Power saving arrangements · CPC title

• H04W56/0035

  detecting errors in frequency or phase · CPC title