Hierarchical Z-Culling (HiZ) Optimization for Texture-Dependent Discard Operations

Patent metadata

Field	Value
Publication number	US-2018082467-A1
Application number	US-201615267631-A
Country	US
Kind code	A1
Filing date	Sep 16, 2016
Priority date	Sep 16, 2016
Publication date	Mar 22, 2018
Grant date	—

Abstract

Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimization for texture-dependent discard operations are described. In an embodiment, a processor performs one or more operations (such as HiZ or Hierarchical Stencil test) on depth data of an image tile in response to a determination that texture space bounds of the image tile is fully opaque. The processor performs the one or more operations regardless of whether a discard operation is enabled. Other embodiments are also disclosed and claimed.

First claim

1 . An apparatus comprising:
memory to store depth data corresponding to an image tile; and a processor, coupled to the memory, to perform one or more operations on the depth data in response to a determination that texture space bounds of the image tile is fully opaque or fully transparent, wherein the processor is to perform the one or more operations regardless of whether a discard operation is enabled.

2 . The apparatus of claim 1 , wherein the one or more operations are to comprise a Hierarchical Z-Culling (HiZ) operation or a hierarchical stencil test.

3 . The apparatus of claim 1 , wherein the processor is to analyze per-texture and per-shader program information.

4 . The apparatus of claim 3 , wherein the processor is to cause storage of the analyzed per-texture and per-shader program information to assist in performance of the one or more operations.

5 . The apparatus of claim 4 , wherein the processor is to modify at least one of the one or more operations based on the stored information.

6 . The apparatus of claim 1 , wherein a fragment shader is to operate on the image tile, wherein the fragment shader is to perform a discard operation that is dependent on an alpha or color channel of a texture or set of textures corresponding to the image tile.

7 . The apparatus of claim 6 , wherein the set of textures have a constant alpha or color channel of 1.

8 . The apparatus of claim 1 , wherein the processor is to cause storage of an alpha interval per texture.

9 . The apparatus of claim 8 , wherein the alpha interval stores a minimum alpha over an entire texture and a maximum alpha over the entire texture.

10 . The apparatus of claim 1 , wherein the processor is to obtain classification information per each texel corresponding to the texture space bounds of the image tile.

11 . The apparatus of claim 10 , wherein the processor is to perform the one or more operations based at least in part on the classification information.

12 . The apparatus of claim 1 , wherein the processor is to perform the one or more operations in response to a determination of whether the texture space bounds of the image tile is transparent.

13 . The apparatus of claim 1 , wherein the depth data is to comprise a minimum depth bound and a maximum depth bound for the tile.

14 . The apparatus of claim 1 , wherein the memory is to comprise a depth buffer.

15 . The apparatus of claim 1 , wherein the image tile is to comprise one or more pixels.

16 . The apparatus of claim 1 , wherein the processor is to comprise a Graphics Processing Unit (GPU) having one or more graphics processing cores.

17 . The apparatus of claim 1 , wherein the processor is to comprise one or more processor cores.

18 . The apparatus of claim 1 , wherein the processor is to comprise at least a portion of the memory.

19 . The apparatus of claim 1 , wherein the processor and the memory are on a single integrated circuit die.

20 . A method comprising:
storing depth data corresponding to an image tile in memory; and performing one or more operations on the depth data in response to a determination that texture space bounds of the image tile is fully opaque or fully transparent, wherein the one or more operations are performed regardless of whether a discard operation is enabled.

21 . The method of claim 20 , wherein the one or more operations comprise a Hierarchical Z-Culling (HiZ) operation or a hierarchical stencil test.

22 . The method of claim 20 , further comprising analyzing per-texture and per-shader program information.

23 . One or more computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
store depth data corresponding to an image tile in memory; and perform one or more operations on the depth data in response to a determination that texture space bounds of the image tile is fully opaque or fully transparent, wherein the processor is to perform the one or more operations regardless of whether a discard operation is enabled.

24 . The computer-readable medium of claim 23 , wherein the one or more operations are to comprise a Hierarchical Z-Culling (HiZ) operation or a hierarchical stencil test.

25 . The computer-readable medium of claim 23 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause analysis of per-texture and per-shader program information.

Assignees

• Intel Corp

Inventors

• Andersson Magnus
• Toth Robert M
• Hasselgren Jon N
• Akenine-Moller Tomas G

Classifications

• G06T15/40

  Hidden part removal · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T15/405 Primary

  using Z-buffer · CPC title

• G06T2210/62

  Semi-transparency · CPC title

• G06T15/04

  Texture mapping · CPC title