Substrate Features for Enhanced Fluidic Assembly of Electronic Devices

Patent metadata

Field	Value
Publication number	US-2018076352-A1
Application number	US-201615266796-A
Country	US
Kind code	A1
Filing date	Sep 15, 2016
Priority date	Sep 15, 2016
Publication date	Mar 15, 2018
Grant date	—

Abstract

Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate.

First claim

1 . A fluidic assembly system, the system comprising:
a substrate including a plurality of wells each having a sidewall and a first width, wherein a through hole via extends from a bottom of at least one of the plurality of wells; a post enhanced diode including a post having a second width and extending from a top surface of a diode structure, and wherein the diode structure has a third width; and wherein the first width is greater than both the second width and the third width, and wherein the post of the post enhanced diode is incapable of insertion in the through hole via.

2 . The system of claim 1 , wherein a width of the through hole via is less than a width of the post.

3 . The system of claim 1 , wherein the through hole via is offset from the post such that when the post enhanced diode is deposited in the well in an inverted orientation the post is incapable of insertion in the through hole via.

4 . The system of claim 3 , wherein the through hole via is offset from a center location of the bottom of the at least one of the plurality of wells.

5 . The system of claim 3 , wherein the post is offset from a center location of the top surface of the diode structure.

6 . The system of claim 1 , wherein the through hole via extends from an out of boundary area of the at least one of the plurality of wells, wherein the out of boundary area incapable of being fully covered by the diode structure when the post enhanced diode is deposited in the well in a non-inverted orientation.

7 . The system of claim 6 , wherein the well has a tear drop shape including a circular region and a triangular region, and wherein the out of boundary area includes a portion of the triangular region.

8 . The system of claim 1 , wherein the sidewall is a sloping sidewall.

9 . The system of claim 1 , wherein the at least one of the plurality of wells has a polygonal shape.

10 . The system of claim 1 , wherein the at least one of the plurality of wells is a first well, and wherein the first well is joined with a second well to make a multi-well structure, and wherein the post enhanced diode may be deposited in a non-inverted orientation in the first well such that it cannot move into the second well without being completely removed from the first well.

11 . The system of claim 1 , wherein the at least one of the plurality of wells is a first well, and wherein the first well is joined with a second well to make a multi-well structure, and wherein the post enhanced diode may be deposited in a non-inverted orientation in the first well but is incapable of being deposited in the second well in the non-inverted orientation.

12 . A fluidic assembly system, the system comprising:
a substrate including a plurality of polygonal wells, wherein each of the polygonal wells have a sidewall defining an outer perimeter of the respective polygonal well and extending from one surface of the substrate to a well bottom, wherein the outer perimeter is a polygon shape, and wherein each of the polygonal wells is sized to accept a single disk shaped device.

13 . The system of claim 12 , wherein the disk shaped device is a diode structure.

14 . The system of claim 12 , wherein the side wall of at least one of the polygonal wells is a sloped sidewall that differentially limits removal of the disk shaped device from the well depending upon orientation of the disk shaped device.

15 . A method for forming a fluidic assembly substrate, the method comprising:
receiving a post dimension of a post enhanced diode; providing a substrate material having a top surface and a bottom surface; forming a plurality of wells in the substrate material, wherein each of the plurality of wells extends only partially into the substrate material, wherein a through hole via extends from a bottom of at least one of the plurality of wells through to the bottom surface of the substrate material; and wherein the through hole via is formed based upon the post dimension such that a post of the post enhanced diode is incapable of insertion into the through hole via.

16 . The method of claim 15 , wherein a width of the through hole via is less than a width of the post.

17 . The method of claim 15 , wherein the shape of the at least one of the wells is polygonal.

18 . The method of claim 15 , wherein the through hole via is located between two adjacent facets of a polygon forming a sidewall of the well.

19 . The method of claim 15 , wherein the through hole via extends from an out of boundary area of the at least one of the plurality of wells, and wherein the out of boundary area is incapable of being fully covered by a circular disk deposited in the well.

20 . The method of claim 19 , wherein the well has a tear drop shape including a circular region and a triangular region, and wherein the out of boundary area includes a portion of the triangular region.

Assignees

• Sharp Laboratories America Inc

Inventors

• Heine David Robert
• Garner Sean Mathew
• Shinde Avinash Tukaram

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W90/00

  Package configurations · CPC title

• H01L33/06

  Electricity · mapped topic

• H01L2933/0033

  Electricity · mapped topic

• H01L33/005 Primary

  Electricity · mapped topic