Array substrate, manufacturing method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-2018046045-A1
Application number	US-201615501424-A
Country	US
Kind code	A1
Filing date	May 5, 2016
Priority date	Feb 2, 2016
Publication date	Feb 15, 2018
Grant date	—

Abstract

The embodiments of the invention disclose an array substrate, a manufacturing method thereof, and a display panel. The array substrate comprises a base substrate, and a first conductive layer, an insulating layer and a second conductive layer arranged on the base substrate sequentially, the insulating layer comprising a via hole region, a semi-retaining region outside the via hole region and a full-retaining region encircling the semi-retaining region and the via hole region. Since the via hole region is surrounded by the semi-retaining region, the thickness of the insulating layer around the via hole is reduced, and thus the influence of the material of the insulating layer left on a rim of the via hole can be reduced. Moreover, since the height difference of the insulating layer is divided into two segments, the influence by height difference in the overall thickness of the insulating layer can be diminished.

First claim

1 . An array substrate, comprising:
a base substrate, and a first conductive layer, an insulating layer and a second conductive layer arranged on the base substrate in sequence, wherein the insulating layer comprises a via hole region, a semi-retaining region outside the via hole region and a full-retaining region encircling a region where the semi-retaining region and the via hole region are located, wherein the via hole region comprises a via hole penetrating the insulating layer, and the second conductive layer is electrically connected with the first conductive layer by means of the via hole, wherein a vertical distance between an upper surface of the semi-retaining region of the insulating layer and an upper surface of the first conductive layer is smaller than that between an upper surface of the full-retaining region of the insulating layer and the upper surface of the first conductive layer.

2 . The array substrate according to claim 1 , wherein the semi-retaining region entirely encircles the via hole region.

3 . The array substrate according to claim 1 , wherein the insulating layer is made of an organic material.

4 . The array substrate according to claim 3 , wherein the insulating layer is made of a photosensitive organic material.

5 . The array substrate according to claim 1 , wherein the semi-retaining region has a width of 1 μm˜6 μm.

6 . The array substrate according to claim 1 , wherein the vertical distance between the upper surface of the semi-retaining region of the insulating layer and the upper surface of the first conductive layer is smaller than or equal to half the vertical distance between the upper surface of the full-retaining region of the insulating layer and the upper surface of the first conductive layer.

7 . The array substrate according to claim 1 , wherein the insulating layer has a thickness of 2 μm˜3 μm in the full-retaining region.

8 . The array substrate according to claim 1 , wherein the first conductive layer is a drain of a thin film transistor in the array substrate, and the second conductive layer is a pixel electrode.

9 . A display panel comprising an array substrate, the array substrate comprising:
a base substrate, and a first conductive layer, an insulating layer and a second conductive layer arranged on the base substrate in sequence, wherein the insulating layer comprises a via hole region, a semi-retaining region outside the via hole region and a full-retaining region encircling a region where the semi-retaining region and the via hole region are located, wherein the via hole region comprises a via hole penetrating the insulating layer, and the second conductive layer is electrically connected with the first conductive layer by means of the via hole, wherein a vertical distance between an upper surface of the semi-retaining region of the insulating layer and an upper surface of the first conductive layer is smaller than that between an upper surface of the full-retaining region of the insulating layer and the upper surface of the first conductive layer.

10 . A manufacturing method for an array substrate, comprising:
forming a first conductive layer on a base substrate; forming an insulating layer on the base substrate on which the first conductive layer has been formed, the insulating layer comprising a via hole region, a semi- retaining region outside the via hole region and a full-retaining region encircling a region where the semi-retaining region and the via hole region are located, wherein the via hole region comprises a via hole penetrating the insulating layer, and a vertical distance between an upper surface of the semi-retaining region of the insulating layer and an upper surface of the first conductive layer is smaller than that between an upper surface of the full-retaining region of the insulating layer and the upper surface of the first conductive layer; forming a second conductive layer on the base substrate on which the insulating layer has been formed, the second conductive layer being electrically connected with the first conductive layer by means of the via hole.

11 . The manufacturing method according to claim 10 , wherein forming an insulating layer on the base substrate on which the first conductive layer has been formed comprises:
forming the insulating layer through a patterning process on the base substrate on which the first conductive layer has been formed.

12 . The manufacturing method according to claim 11 , wherein the insulating layer is made of a photosensitive organic material.

13 . The manufacturing method according to claim 12 , wherein forming the insulating layer through a patterning process on the base substrate on which the first conductive layer has been formed comprises:
forming an insulating film on the base substrate on which the first conductive layer has been formed; patterning the insulating film by using a first mask plate, to form the full-retaining region of the insulating layer in a region of the insulating film corresponding to a first region of the first mask plate, the semi-retaining region of the insulating layer in a region of the insulating film corresponding to a second region of the first mask plate, and the via hole region of the insulating layer in a region of the insulating film corresponding to a third region of the first mask plate.

14 . The manufacturing method according to claim 13 , wherein the first mask plate is selected from a group consisting of a half-tone mask plate and a grey tone mask plate.

15 . The manufacturing method according to claim 13 , wherein the photosensitive organic material is a positively photosensitive material, and the first region of the first mask plate is a light shielding region, the second region of the first mask plate is a partially light-transmissive region, and the third region of the first mask plate is a completely light-transmissive region.

16 . The manufacturing method according to claim 13 , wherein the photosensitive organic material is a negatively photosensitive material, and the first region of the first mask plate is a completely light-transmissive region, the second region of the first mask plate is a partially light-transmissive region, and the third region of the first mask plate is a light shielding region.

17 . The display panel according to claim 9 , wherein the semi-retaining region entirely encircles the via hole region.

18 . The display panel according to claim 9 , wherein the insulating layer is made of a photosensitive organic material.

19 . The display panel according to claim 9 , wherein the vertical distance between the upper surface of the semi-retaining region of the insulating layer and the upper surface of the first conductive layer is smaller than or equal to half the vertical distance between the upper surface of the full-retaining region of the insulating layer and the upper surface of the first conductive layer.

20 . The display panel according to claim 9 , wherein the first conductive layer is a drain of a thin film transistor in the array substrate, and the second conductive layer is a pixel electrode.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Chen Cheng
• Li Jilong
• Xu Dezhi
• Lv Yanming

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• G02F1/136227 Primary

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/136259

  Repairing; Defects · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title