Transmitter circuit, semiconductor apparatus and data transmission method

Patent metadata

Field	Value
Publication number	US-2018041233-A1
Application number	US-201715727968-A
Country	US
Kind code	A1
Filing date	Oct 9, 2017
Priority date	Mar 17, 2015
Publication date	Feb 8, 2018
Grant date	—

Abstract

The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

First claim

What is claimed is:

1 . A transmitter circuit comprising:
a pulse generating circuit generating a pulse signal based on edges of input data; a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element; a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element; and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on, wherein the output stop circuit includes: a first capacitor element connected between a power supply and a first node; a first transistor connected between the first node and a ground; a second transistor connected between the power supply and a second node; and a second capacitor element connected between the second node and the ground, wherein a gate of the first transistor is connected to the second node and a gate of the second transistor is connected to the first node, and the stop of the output of the first and second output pulse signals is released in accordance with a voltage of the first node and a voltage of the second node.

2 . The transmitter circuit according to claim 1 , wherein the first transistor is an N-type transistor and the second transistor is a P-type transistor.

3 . The transmitter circuit according to claim 2 , wherein
a source of the first transistor is connected to the ground and a drain of the first transistor is connected to the first node, and a source of the second transistor is connected to the power supply and a drain of the second transistor is connected to the second node.

4 . A transmitter circuit comprising:
a pulse generating circuit generating a pulse signal based on edges of input data; a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element; a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element; and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on, wherein the output stop circuit includes: a capacitor element connected to one of a power supply and a ground; and a resistor element connected to other one of the power supply and the ground, wherein the stop of the output of the first and second output pulse signals is released in accordance with a voltage of a connection node between the capacitor element and the resistor element.

5 . The transmitter circuit according to claim 4 , wherein the prescribed period is determined by a time constant of the capacitor element and the resistor element.

Assignees

• Renesas Electronics Corp

Inventors

• Takeda Koichi
• Nagase Hirokazu
• Watanabe Shinpei

Classifications

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H04B5/0075

  Electricity · mapped topic

• H04L25/0266 Primary

  Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling · CPC title