Dynamic predictor of semiconductor lifetime limits

Patent metadata

Field	Value
Publication number	US-2018038906-A1
Application number	US-201615230067-A
Country	US
Kind code	A1
Filing date	Aug 5, 2016
Priority date	Aug 5, 2016
Publication date	Feb 8, 2018
Grant date	—

Abstract

A method and circuit of monitoring an effective age of a target circuit are provided. A standby mode is activated in the target circuit. A standby current of a first number of circuit blocks of the target circuit is measured. The measured standby current of the first number of circuit blocks is compared to a first baseline standby current of the first number of circuit blocks. Upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of a baseline standby current of the first number of circuit blocks, the first number of circuit blocks is identified to have a bias temperature instability (BTI) degradation concern.

First claim

What is claimed is:

1 . A method of monitoring an effective age of a target circuit, comprising:
activating a standby mode in the target circuit; measuring a standby current of a first number of circuit blocks of the target circuit; comparing the measured standby current of the first number of circuit blocks to a first baseline standby current of the first number of circuit blocks; and upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of the first baseline standby current of the first number of circuit blocks, identifying the first number of circuit blocks to have a bias temperature instability (BTI) degradation concern, wherein the first predetermined factor is <1.

2 . The method of claim 1 , wherein the standby mode is activated in the first number of circuit blocks of the target circuit.

3 . The method of claim 2 , wherein activating the standby mode comprises at least one of:
(i) turning OFF a system clock; and (ii) disabling any data input to the target circuit.

4 . The method of claim 1 , further comprising:
measuring a standby current of a second number of circuit blocks of the target circuit; comparing the measured standby current of the second number of circuit blocks to a second baseline standby current of the second number of circuit blocks; and upon determining that the measured standby current of the second number of circuit blocks is above a second predetermined factor of the second baseline standby current, identifying the second number of circuit blocks to have a time dependent dielectric breakdown (TDDB) degradation concern, wherein the second predetermined factor is >1.

5 . The method of claim 4 , further comprising:
measuring a noise of the standby current of the second number of circuit blocks; comparing the measured noise of the standby current of the second number of circuit blocks to a predetermined threshold; and upon determining that the measured noise of the standby current of the second number or circuit blocks is above the predetermined threshold, identifying the second number of circuit blocks to have the time dependent dielectric breakdown (TDDB) degradation concern.

6 . The method of claim 5 , further comprising:
upon identifying that the first number of circuit blocks has the BTI degradation concern, imposing one or more restrictions on the first number of circuit blocks to prevent a premature failure of the first number of circuit blocks; and upon identifying that the second number of circuit blocks has the TDDB degradation concern, imposing one or more restrictions on the second number of circuit blocks to prevent a premature failure of the second number of circuit blocks.

7 . The method of claim 4 , wherein a number of circuit blocks that are included in the second number of circuit blocks is based on maintaining a total standby current consumption of the second number of circuit blocks below a predetermined ratio of the total standby current consumption to a target current measurement sensitivity.

8 . The method of claim 7 , wherein the predetermined ratio of the total standby current consumption to the target current measurement sensitivity is at most 100:1.

9 . The method of claim 4 , wherein a number of circuit blocks that are included in the first number of circuit blocks is larger than a number of circuit blocks that are included in the second number of circuit blocks.

10 . The method of claim 1 , further comprising comparing a signature of a current consumption over a predetermined time period of the first number of circuit blocks to a stored aging model of the first number of circuit blocks to identify an effective age of the first number of circuit blocks.

11 . The method of claim 10 , further comprising adjusting the stored aging model of the first number of circuit blocks based on a deviation between the signature of the current consumption over the predetermined time period of the first number of circuit blocks and the stored aging model of the first number of circuit blocks.

12 . A method of monitoring an effective age of a target circuit, comprising:
activating a standby mode in the target circuit; measuring a standby current of a second number of circuit blocks of the target circuit; comparing the measured standby current of the second number of circuit blocks to a second baseline standby current of the second number of circuit blocks; measuring a noise of the standby current of the second number of circuit blocks; and upon determining that at least one of: (i) the measured standby current of the second number of circuit blocks is above a second predetermined factor of the second baseline standby current, wherein the second predetermined factor is >1, and (ii) the measured noise of the standby current of the second number or circuit blocks is above a predetermined threshold, identifying the second number of circuit blocks to have a time dependent dielectric breakdown (TDDB) degradation concern.

13 . The method of claim 12 , wherein the standby mode is activated in the second number of circuit blocks of the target circuit.

14 . The method of claim 13 , wherein activating the standby mode comprises at least one of:
(iii) turning OFF a system clock; and (iv) disabling any data input to the target circuit.

15 . The method of claim 12 , further comprising:
measuring a standby current of a first number of circuit blocks of the target circuit; comparing the measured standby current of the first number of circuit blocks to a first baseline standby current of the first number of circuit blocks; and upon determining that the measured standby current of a first number of circuit blocks is below a first predetermined factor of the first baseline standby current of the first number of circuit blocks, identifying the first number of circuit blocks to have a bias temperature instability (BTI) degradation concern, wherein the first predetermined factor is <1.

16 . The method of claim 15 , further comprising:
upon identifying that the first number of circuit blocks has the BTI degradation concern, imposing one or more restrictions on the first number of circuit blocks to prevent a premature failure of the first number of circuit blocks; and upon identifying that the second number of circuit blocks has the TDDB degradation concern, imposing one or more restrictions on the second number of circuit blocks to prevent a premature failure of the second number of circuit blocks.

17 . The method of claim 12 , wherein a number of circuit blocks that are included in the second number of circuit blocks is based on maintaining a total standby current consumption of the second number of circuit blocks below a predetermined ratio of the total standby current consumption to a target current measurement sensitivity.

18 . The method of claim 17 , wherein the predetermined ratio of the total standby current consumption to the target current measurement sensitivity is at most 100:1.

19 . An age monitor circuit comprising:
a controller circuit coupled to a target circuit and configured to activate a standby mode in the target circuit; a test circuit coupled to the controller circuit; a register circuit coupled to the test circuit; and a predictor circuit coupled to the register circuit, wherein:
the controller circuit is configured to activate a standby mode in the target circuit and select a first number of circuit blocks of the target circuit; and
the test circuit is c

Assignees

• IBM

Inventors

• Cher Chen Yong
• Jenkins Keith A
• Linder Barry P

Classifications

• G01R31/2849 Primary

  Environmental or reliability testing, e.g. burn-in or validation tests (of individual semiconductors G01R31/2642; of printed circuits boards G01R31/2817; of IC's G01R31/2855) · CPC title

• G01R31/2837

  Characterising or performance testing, e.g. of frequency response (transient response G01R27/28) · CPC title

• G01R31/282 Primary

  Testing of electronic circuits specially adapted for particular applications not provided for elsewhere (G01R31/2801 and G01R31/2851 take precedence) · CPC title